Non-Inverting Buffers. 54HC4050 Datasheet

54HC4050 Buffers. Datasheet pdf. Equivalent

54HC4050 Datasheet
Recommendation 54HC4050 Datasheet
Part 54HC4050
Description CMOS Logic Hex Non-Inverting Buffers
Feature 54HC4050; CMOS Logic Hex Non-Inverting Buffers 54HC4050 Logic Diagram Memory FEATURES: • High speed CMOS l.
Manufacture Maxwell
Datasheet
Download 54HC4050 Datasheet




Maxwell 54HC4050
54HC4050
CMOS Logic Hex
Non-Inverting Buffers
FEATURES:
• High speed CMOS logic hex non-inverting buffers
• RAD-PAK® radiation hardened against natural space radia-
tion
• Single Event Effects:
- SEL: > 120 MeV/mg/cm2
• Total dose hardness:
• - > 100 Krad (Si), depending upon space mission
• Package:
-16 Pin RAD-PAK® Flat Pack
• Typical propagation delay:
- 6ns at VCC = 5V, CL = 15pF, TA = 25°C
• High-to-Low voltage level converter for up to VI = 16V
• Fanout (over temperature range)
-10 LSTTL loads (Standard Outputs)
-15 LSTTL loads (Bus Driver Outputs)
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• 2V to 6V operation
• High noise immunity
• -NIL = 30%, NIH = 30% of VCC at VCC = 5V
Logic Diagram
DESCRIPTION:
Maxwell Technologies' 54HC4050 high speed CMOS Logic
Hex Non-Inverting Buffers features a greater than 100 krad(Si)
total dose tolerance, depending upon space mission. These
parts have a modified input protection structure that enables
them to be used as logic level translators which will convert
high-level logic to a low-level logic while operating off the low-
level logic supply. For example, 15V input pulse levels can be
down-converted to 0V to 5V logic levels. The modified input
protection structure protects the input from negative electro-
static discharge. The 54HC4050 can be used as simple buff-
ers or inverters without level translation.
Maxwell Technologies' patented RAD-PAK® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, RAD-PAK provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
1000587
12.19.01 Rev 1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice 1
©2001 Maxwell Technologies.
All rights reserved.



Maxwell 54HC4050
CMOS Logic Hex Non-Inverting Buffers
54HC4050
TABLE 1. 54HC4050 PINOUT DESCRIPTIONS
PIN SYMBOL
DESCRIPTION
1
8
13, 16
3, 5, 7, 9, 11, 14
2
4
6
10
12
15
VCC
VSS
NC
A-F
G=A
H=B
I=C
J=D
K=E
L=F
Power supply
Ground
Not Connected
Inputs
Buffered Output
Buffered Output
Buffered Output
Buffered Output
Buffered Output
Buffered Output
TABLE 2. 54HC4050 ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
Storage Temperature
Operating Temperature Range
DC Supply Voltage
DC Input Diode Current
For VI < -0.5V or VI > VCC +0.5V
DC Output Diode Current
For VO < -0.5V or VO > VCC +0.5V
DC Output Source or Sink Current per Output Pin
For VO > -0.5V or VO < VCC +0.5V
DC VCC or Ground Current
TS
TA
VCC
IIK
IOK
IO
ICC or IGND
-65
-55
-0.5
-20
-20
-25
-50
MAX
150
125
7.0
+20
+20
+25
+50
UNIT
°C
°C
V
mA
mA
mA
mA
TABLE 3. DELTA LIMITS
PARAMETER
VARIATION
ICC ±10% of specified value in Table 5
1000587
12.19.01 Rev 1
All data sheets are subject to change without notice 2
©2001 Maxwell Technologies.
All rights reserved.



Maxwell 54HC4050
CMOS Logic Hex Non-Inverting Buffers
54HC4050
TABLE 4. 54HC4050 RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
Supply Voltage
DC Input or output Voltage
Input Rise and Fall Time
2V
4.5V
6V
Temperature Range
VCC 2
6
VI, VO
0
VCC
--
1000
500
400
TA -55 125
UNIT
V
V
ns
°C
PARAMETER
TABLE 5. 54HC4050 DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
SYMBOL
TEST CONDITIONS
MIN
High Level Output Voltage
CMOS Loads
High Level Output Voltage
TTL Loads
VOH VI = VIH or VIL, IO = -0.02mA
VCC = 2V
VCC = 4.5V
VCC = 6V
VI = VIH or VIL, IO = -4mA
VCC = 4.5V
+25°C
-55 to 125°C
1.9
4.4
5.9
3.98
3.7
VI = VIH or VIL, IO = -5.2mA
+25°C
VCC = 6V
-55 to 125°C
5.48
5.2
Low Level Output Voltage
CMOS Loads
Low Level Output Voltage
TTL Loads
VOL VI = VIH or VIL, IO = -0.02mA
VCC = 2V
VCC = 4.5V
VCC = 6V
VI = VIH or VIL, IO = 4mA
VCC = 4.5V
+25°C
-55 to 125°C
0.26
0.4
VI = VIH or VIL, IO = 5.2mA
VCC = 6V
+25°C
-55 to 125°C
0.36
0.4
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
VIH VCC = 2V
VCC = 4.5V
VCC = 6V
VIL VCC = 2V
VCC = 4.5V
VCC = 6V
II VCC = 6V, VI = VCC or GND
+25°C
-55 to 125°C
1.5
3.15
4.2
--
--
--
--
--
VCC = 6V, VI = 15V
+25°C
-55 to 125°C
--
--
MAX
--
--
--
--
--
--
0.1
0.1
0.1
--
--
--
--
--
--
--
0.5
1.35
1.8
±0.1
±1
±0.5
±5
UNIT
V
V
V
V
µA
1000587
12.19.01 Rev 1
All data sheets are subject to change without notice 3
©2001 Maxwell Technologies.
All rights reserved.





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)