SP5669

SP5669 2.7GHz I2C Bus Controlled Synthesiser Preliminary Information DS4852 Issue 2.1 May 1999 Features q q q q q q q q q q Ordering Information SP5669/KG/MP1S (Tubes) SP5669/KG/MP1T (Tape and reel) Complete 2.7GHz single chip system Compatible with UK DTT offset requirements Optimised for low phase noise Selectable divide by two prescaler Selectable reference division ratio Selectable reference/comparison frequency output Selectable charge pump current Four selectable I2C bus address 5–level ADC Pin compatible with the SP5658 3–wire bus controlled synthesiser and SP5659 I2C bus synthesiser and SP5659 I2C bus synthesiser ESD protection; (Normal ESD handling procedures should be observed) The comparison frequency is obtained either from an on–chip crystal controlled oscillator, or from an external source. The oscillator frequency Fref or the comparison frequency Fcomp may be switched to the REF/COMP output. This feature is ideally suited to providing the reference frequency for a second synthesiser such as in a double conversion tuner (see Fig. 8). The synthesiser is controlled via an I 2 C bus, and responds to one of four programmable addresses which are selected by applying a specific voltage to the ‘address’ input. This feature enables two or more synthesisers to be used in a system. The device contains four switching ports P0–P3 and a 5–level ADC. The output of the ADC can be read via the I2 C bus. The device also contains a varactor line disable and chargepump disable...