Document
SP8782A & B
SP8782A & B
1GHz ÷ 16/17, ÷32/33 Multi-Modulus Divider
DS3651 Issue 2.4 June 1999
Features
q q q q
Advanced Resynchronisation techniques to negate loop delay effects CMOS compataible output capability Multi-Modulus division Available as DESC SMD 5962-9208901MPA
Odering Information
SP8782 A DG SP8782 B MP DES9208901/AC/DGAZ(SMD)
Description
The SP8782 is a multi-modulus divider which divides by 16/ 17 when the Ratio Select input is low and by 32/33 when theRatio Select input is high. When high, the modulus Control input selects the lower division ratio (16 or 32) and the higher ratio (17 or 33) when it is low. The device uses resynchronisation techniques to reduce the effects of propagation delays in frequency synthesis. The SP8782A (ceramic DIL package) is characterised over the full military temperature range of -55°C to +125°C, the SP8782B (miniature plastic DIL package) over the industrial range of -40°C to+85°C.
Absolute Maximum Ratings
Supply Voltage Clock input level Junction temperature Storage temperature range: SP8782A SP8782B 6V 2.5V p-p +175°C -55°C to +150°C -55°C to +125°C
RATIO SELECT 1
VCC 2
CLOCK INPUT CLOCK INPUT
2 3 ÷ 16/17 ÷ 32/33 7 OUTPUT
4 VEE
5 MODULUS CONTROL INPUT
Figure 1 Functional Diagram
1
SP8782A & B
RATIO SELECT CLOCK INPUT CLOCK INPUT VEE
1 2 3 4
8 7 6 5
VCC OUTPUT NC MODULUS CONTROL
DG 8
RATIO SELECT CLOCK INPUT CLOCK INPUT VEE 1 2 3 4 8 7 6 5 VCC OUTPUT NC MODULUS CONTROL
MP 8
Figure 2 Typical Pin Connections
Electrical Characteristics
Unless otherwise stated, the Electrical Characteristics are guaranteed over the specified supply, frequency and temperature range. Supply Voltage, VCC = +4V to +5.5V, VEE = 0V Temperature Tamb= -55°C to +125°C, (SP8782A), -40°C to +85° C (SP8782B)
Characteristic
Maximum frequency (sinewave input) Minimum frequency Min Slew rate for low frequency operation Power Supply current, ICC Output low voltage Output high voltage Modulus control input high voltage Modulus control input low voltage Modulus control input high current Modulus control input low current Ratio select input high voltage Ratio selected input low voltage Ratio select input current Clock to output propagation Delay Set-up time, ts Release time,tr
Pin
2, 3 2, 3 2, 3 8 7 7 5 5 5 5 1 1 1 2,3,7 5,7 5,7
Value
Min
1 50 100 60 1.7 VCC VCC 0.3VCC 1.2 -1.2 VCC 0.4VCC 10 3
Conditions
Max Units
GHz MHz V/µs mA V V V V mA mA V V µA ns ns ns Input = 200-1200mVp-p Input = 400-1200mVp-p Output unloaded, VCC=5.5V
0 VCC-1.4 0.7VCC 0 0.6 -0.6 0.6VCC 0 -10 3 3
At driver end of 3kΩ resistor At driver end of 3kΩ resistor Via 3kΩ resistor to VCC Via 3kΩ resistor to VCC
See note 1 and Fig. 3a See note 2 and Fig. 3b
Notes: 1. The set-up time ts is defined as the minimum time that can elapse between L→H transition of the modulus control input and the next L→H output transition to ensure that the ÷ 16 (32) mode is obtained. 2. The release time tr is defined as the minimum time that can elapse between H→L transition of the modulus control input and the next L→H output transition to ensure that the ÷ 17 (33) mode is obtained.
2
SP8782A & B
Modulus control input 0 1
Ratio select input 0 1 ÷17 ÷16 ÷33 ÷32
Table 1 Truth table for control inputs
CLOCK INPUT
t s
MODULUS CONTROL INPUT DON’T CARE
t s
DON’T CARE
9 (17) OUTPUT 8 (16)
8 (16) 8 (16) DIVIDE-BY-16 (32) MODE ESTABLISHED
Fig. 3a Setting divide-by-16 Figure 3a Setting divide - by - 16 (32 mode) (32) mode
CLOCK INPUT
t r
MODULUS CONTROL INPUT DON’T CARE
t r
DON’T CARE
8 (16) OUTPUT 8 (16)
9 (17) EXTRA PULSE 8 (16)
DIVIDE-BY-17 (33) MODE ESTABLISHED
Figure 3b Setting divide - by - 17 (33 mode)
Figure 3 Timing diagrams
3
SP8782A & B
1600 1400
INPUT AMPLITUDE (mV p-p)
1200 1000
* Tested as specified
800 600 400 200 0
GUARANTEED OPERATING WINDOW
*
in table of Electrical *Tested as speci Characteristics in table of E Characteristi
0
200 400 INPUT FREQUENCY (MHz)
600
800
Figure 4 Typical input characteristics
RATIO SELECT 1 6 8 V CC 10n
MODULUS CONTROL INPUT CLOCK INPUT
3k
5 7 OUTPUT
1n 2
NOTES 1. Pin 6 is grounded to improve isolation between the output and the NOTES modulus control input. 1n 3k Ωgrounded resistor on pin5 reduces 1. 2.The Pin 6 is to improve the amplitude of the moduluscontrol isolation the output and signal to between minimise radiation. the modulus control input 2. The 3kΩ resistor on pin 5 reduces the amplitude of the modulus control signal to minimise radiation
DIVIDE BY DIVIDE BY 32/33 16/17 16/17 OR OR 32/33
3
4 V EE
Figure 5 Typical application showing interfacing
4
SP8782A & B
j1 j 0.5 j2
j 0.2
1100
j5
0
0.2
0.5
1000
1
2
5
800
200
2 j5
2 j 0.2
600
400
2 j 0.5 2 j1
2 j2
Figure 6 Typical input impedance. Test conditions: supply voltage =5V, ambient temperature =25°C, frequencies in MHz, impedances normalised to 50Ω
5
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