SPC5200CBV400

Freescale Semiconductor, Inc. MPC5200/D Rev. 2, 5/2004 MPC5200 Hardware Specifications Topic Page NOTE: Freescale Semiconductor, Inc... 1 2 3 4 5 6 7 Overview ......................................1 Features .......................................1 Electrical and Thermal Characteristics..............................5 Package Description ..................60 System Design Information ........69 Ordering Information ..................74 Document Revision History ........75 The information in this document is subject to change. For the latest data on the MPC5200, visit www.mobilegt.com and proceed to the MPC5200 Product Summary Page. 1 Overview The MPC5200 integrates a high performance MPC603e series G2_LE core with a rich set of peripheral functions focused on communications and systems integration. The G2_LE core design is based on the PowerPC® core architecture. MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded G2_LE core. The MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers (PSC), I2C, SPI, CAN, J1850, Timers, and GPIOs. 2 Features MPC603e series G2_LE core — — — — — — — — — — — Superscalar architecture 760 MIPS at 400 MHz (-40 to +85 oC) 16 k Instruction cache, 16 k Data cache Double precision FPU Instruction and Data MMU Standard and Critical interrupt capability up...