D-Type Flip-Flops. 7474 Datasheet

7474 Flip-Flops. Datasheet pdf. Equivalent

7474 Datasheet
Recommendation 7474 Datasheet
Part 7474
Description Dual Positive-Edge-Triggered D-Type Flip-Flops
Feature 7474; DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs .
Manufacture Fairchild
Datasheet
Download 7474 Datasheet





Fairchild 7474
September 1986
Revised July 2001
DM7474
Dual Positive-Edge-Triggered D-Type Flip-Flops
with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D-type flip-flops with complementary outputs. The
information on the D input is accepted by the flip-flops on
the positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated. A LOW logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM7474M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
DM7474N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK
D
Q
Q
LHXXHL
HLXXLH
L L XXHH
(Note 1) (Note 1)
HH HH L
HHL LH
H H L X Q0 Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↑ = Positive-going transition of the clock.
Q0 = The output logic level of Q before the indicated input conditions were
established.
Note 1: This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to their inactive (HIGH) level.
© 2001 Fairchild Semiconductor Corporation DS006526
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Fairchild 7474
Absolute Maximum Ratings(Note 2)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
5.5V
0°C to +70°C
65°C to +150°C
Note 2: The Absolute Maximum Ratingsare those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditionstable will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
Min
VCC Supply Voltage
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 4)
tW
Pulse Width
Clock HIGH
(Note 4)
Clock LOW
4.75
2
0
30
37
Clear LOW
30
Preset LOW
30
tSU
Input Setup Time (Note 3)(Note 4)
20
tH
Input Hold Time (Note 3)(Note 4)
5
TA Free Air Operating Temperature
0
Note 3: The symbol () indicates the rising edge of the clock pulse is used for reference.
Note 4: TA = 25°C and VCC = 5V.
Nom
5
Max
5.25
0.8
0.4
16
15
70
Units
V
V
V
mA
mA
MHz
ns
ns
ns
°C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min Max
(Note 5)
VI Input Clamp Voltage
VCC = Min, II = −12 mA
VOH HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
IIH HIGH Level
VCC = Max
D
Input Current
VI = 2.4V
Clock
Clear
1.5
2.4 3.4
0.2 0.4
1
40
80
120
Preset
40
IIL LOW Level
Input Current
VCC = Max
VI = 0.4V
(Note 8)
D
Clock
Clear
1.6
3.2
3.2
Preset
1.6
IOS Short Circuit Output Current VCC = Max (Note 6)
ICC Supply Current
VCC = Max (Note 7)
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time.
18 55
17 30
Note 7: With all outputs open, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.
Note 8: Clear is tested with preset HIGH and preset is tested with clear HIGH.
Units
V
V
V
mA
µA
mA
mA
mA
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Fairchild 7474
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
fMAX
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
Maximum Clock
Frequency
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
From (Input)
To (Output)
Preset to Q
Preset to Q
Clear to Q
Clear to Q
Clock to Q or Q
Clock to Q or Q
RL = 400, CL = 15 pF
Min Max
15
40
25
40
25
40
25
Units
MHz
ns
ns
ns
ns
ns
ns
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