CY7C4804V25

sure C025/0251 PRELIMINARY CY7C4808V25 CY7C4806V25 CY7C4804V25 2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO with Bus Matching Features High-speed, low-power, unidirectional, First-in First-out (FIFO) memories with bus-matching capabilities 64K × 80 (CY7C4808V25) 16K × 80 (CY7C4806V25) 4K × 80 (CY7C4804V25) 2.5V ± 100 mV power supply All I/Os are 1.5V HSTL Individual clock frequency up to 200 MHz (5-ns Read/Write cycle times) High-speed access with tA = 3.8 ns Bus matching on both ports: ×80, ×40, ×20, ×10 Free-running CLKA and CLKB. Clocks may be asynchronous or coincident Cypress standard or First-Word Fall-Through modes Serial and parallel programming of Almost Empty/Full flags, each with three default values (8, 16, 64) Master and partial reset capability Retransmit capability Big or Little Endian format 288 FBGA 19 mm × 19 mm (1.0-mm ball pitch) packaging Width and depth expansion capability Fabricated using Cypress 0.21-micron CMOS technology for optimum speed/power Preliminary Top-level Block Diagram CLKA CSA ENA SIZE1A SIZE2A Bus Matching Output Register Bus Matching Input Register 4K/16K/64K×80 Write Data Path Logic Read Data Path Logic Port A Control Logic CLKB CSB ENB BE/FWFT SIZE1B SIZE2B RT/SPM OE Port B Control Logic A79–0 80 Dual-ported Memory Array 80 B79–0 Write Pointer Read Pointer MR PR FF/IR AF FIFO Reset Logic Status Flag Logic EF/OR AE TDO FS0/SD FS1/SEN Programmable Flag Offset Registers JTAG ...