Integration Sensor. CCD5061 Datasheet

CCD5061 Sensor. Datasheet pdf. Equivalent

Part CCD5061
Description 6K x 128 Element / TDI-Time / Delay and Integration Sensor
Feature PRELIMINARY DATA SHEET CCD5061 6K x 128 Element TDI – Time, Delay and Integration Sensor FEATURES •.
Manufacture Fairchild
Datasheet
Download CCD5061 Datasheet



CCD5061
PRELIMINARY DATA SHEET
CCD5061
6K x 128 Element
TDI – Time, Delay and Integration Sensor
FEATURES
6144 pixels per line
128 lines of integration
8.75µm x 8.75µm pixel size
# of TDI stages selectable from 128, 64, 32,
16, 8, 4
Bi-directional TDI line shifting (shift up or
down)
4 outputs—each capable of 20MHz data
rate—80MHz total data rate
100% fill factor
On-chip binning capability
GENERAL DESCRIPTION
The CCD5061 is a 6144 pixel x 128 line,
high speed TDI sensor. The active imaging
area is organized as 6144 vertical columns
and 128 horizontal TDI rows. The array is
set up for bi-directional operation. There are
identical output registers and amplifiers on
both the top and the bottom of the array.
The outputs to be used (either top or
bottom) are user-selectable and controlled
by the vertical clock phasing. In addition,
the exposure level can be controlled by
reducing the number of TDI rows from 128
to 64, 32, 16, 8 or 4. This is also user-
selectable and is accomplished by supplying
the appropriate phasing for the vertical
clocks within each section. For instance, if
64 lines of TDI were required, the vertical
clocks for lines 65-128 would be connected
to a high potential, which would drain these
unused rows out to the opposite side
(unused) of the array to be dumped in the
drain. With four outputs, each running at
20MHz, the CCD5061 can provide a total
data rate of 80MHz enabling the CCD to run
at better than 12KHz line rate. Utilizing
Fairchild Imaging proprietary buried channel
CCD process, the CCD5061 achieves
consistent, superior TDI performance.
The active imaging area is separated from
the four horizontal output registers by 21
isolation rows. These isolation rows are
covered by a metal lightshield to protect
them while charge transfers to the output
registers. Both the active imaging area and
the isolation region utilize 3-phase clocking.
The four horizontal output registers utilize 4-
phase clocking. Special design techniques
have been implemented to maximize charge
transfer efficiency especially at low light
levels. The output amplifier is a 3-stage
source follower configuration. This allows
maximum scale factor (charge to voltage
conversion) and maximum bandwidth.
The CCD5061 is housed in a custom 176
pin (100 mil grid) ceramic PGA package. It
has an AR coated window.
FUNCTIONAL DESCRIPTION
The following functional elements are
illustrated in the block diagram:
Image Sensing Elements: These are
elements of a line of 6144 image sensors
separated by channel stops and covered by
a passivation layer. Incident photons pass
through a transparent polycrystalline silicon
gate structure creating electron hole pairs.
The resulting photoelectrons are collected in
the photosites during the integration period.
The amount of charge accumulated in each
photosite is a linear function of the localized
incident illumination intensity and integration
period.
Transfer Gates: This gate is a structure
adjacent to the row of image sensor
elements. The charge packets accumulated
in the photosites are transferred in parallel
via the transfer gate to the transport shift
1801 McCarthy Blvd., Milpitas CA 95035; (800) 325-6975; Fax (408) 435-7352; www.fairchildimaging.com Page 1 of 17



CCD5061
PRELIMINARY DATA SHEET
CCD5061
6K x 128 Element
TDI – Time, Delay and Integration Sensor
registers whenever the transfer gate voltage
goes high.
Shift Registers: The vertical shift register
is 3-phase and the horizontal shift register is
4-phase.
Time Delay and Integration: This function
is accomplished by scanning the image
scene across the array at the same rate as
the vertical shift register moves the signal
charge. This results in an effective increase
in the integration time.
Output Amplifier: The CCD5061 is
designed for either uni-directional for bi-
directional operation. There are four
identical output registers and amplifiers on
both the top and bottom of the array. There
are three-stage source follower amplifiers
with a reset MOSFET tied to the input gate.
Charge packets are clocked to a pre-
charged capacitor whose potential changes
linearly in response to the number of
electrons delivered. This potential is applied
to the input gate of an NMOS amplifier
producing a signal at the output Vout pin.
The capacitor is reset with φR to a pre-
charge level prior to the arrival of the next
charge packet except when horizontally
binning. It is reset by use of the reset
MOSFET.
The output amplifier drain is tied to VDD.
The source is connected to an external load
resistor to ground. The source constitutes
the video output from the device.
DEFINITION OF TERMS
Charge-Coupled Device: A charge-
coupled device is a monolithic silicon
structure in which discrete packets of
electron charge are transported from
position to position by sequential clocking of
an array of gates.
Isolation Rows: There are 21 isolation
rows between the image area and the
horizontal shift register. These non-imaging
rows are used as buffer rows to eliminate
crosstalk to the horizontal shift register.
Dynamic Range: The ratio of saturation
output voltage to RMS noise in the dark.
The peak-to-peak random noise is 4-6 times
the RMS noise output.
RMS Noise Equivalent Exposure: The
exposure level that gives an output signal
equal to the RMS noise level at the output in
the dark.
Saturation Exposure: The minimum
exposure level that produces an output
signal corresponding to the maximum
photosite charge capacity. Exposure is
equal to the product of light intensity and
integration time.
Charge Transfer Efficiency: Percentage
of valid charge information that is transferred
between each successive stage of the
transport register.
Responsivity: The output signal voltage
per unit of exposure.
Photo-Response Non-Uniformity: The
difference of the response levels between
the most and the least sensitive regions
under uniform illumination (excluding
blemished elements) expressed as a
percentage of the average response.
Dark Signal: The output signal caused by
thermally generated electrons. Dark signal
is a linear function of integration time and an
exponential function of chip temperature.
Integration Time: The time interval
between the falling edges of any two
successive transfer pulses is the integration
time shown in the timing diagram. The
integration time is the time allowed for the
photosites to collect charge.
Pixel: Picture element or sensor element,
also called photoelement or photosite.
1801 McCarthy Blvd., Milpitas CA 95035; (800) 325-6975; Fax (408) 435-7352; www.fairchildimaging.com Page 2 of 17





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