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SDRAM DIMM. HYMD564646Axx Datasheet

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SDRAM DIMM. HYMD564646Axx Datasheet






HYMD564646Axx DIMM. Datasheet pdf. Equivalent




HYMD564646Axx DIMM. Datasheet pdf. Equivalent





Part

HYMD564646Axx

Description

Unbuffered DDR SDRAM DIMM



Feature


www.DataSheet4U.com 64Mx64 bits Unbuffe red DDR SDRAM DIMM HYMD564646A(L)8-M/K /H/L DESCRIPTION Preliminary Hynix HYM D564646A(L)8-M/K/H/L series is unbuffer ed 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules(DIMMs ) which are organized as 64Mx64 high-sp eed memory arrays. Hynix HYMD564646A(L) 8-M/ K/H/L series consists of eight 64M x8 DDR SDRAM in 40.
Manufacture

Hynix

Datasheet
Download HYMD564646Axx Datasheet


Hynix HYMD564646Axx

HYMD564646Axx; 0mil TSOP II packages on a 184pin glass- epoxy substrate.Hynix HYMD564646A(L)8-M /K/H/L series provide a high performanc e 8-byte interface in 5.25" width form factor of industry standard. It is suit able for easy interchange and addition. Hynix HYMD564646A(L)8-M/K/H/L series i s designed for high speed of up to 133M Hz and offers fully synchronous operati ons referenced to .


Hynix HYMD564646Axx

both rising and falling edges of differe ntial clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data s trobes and Write data masks inputs are sampled on both rising and falling edge s of it. The data paths are internally pipelined and 2-bit prefetched to achie ve very high bandwidth. All input and o utput voltage leve.


Hynix HYMD564646Axx

ls are compatible with SSTL_2. High spee d frequencies, programmable latencies a nd burst lengths allow variety of devic e operation in high performance memory system. Hynix HYMD564646(L)8-M/K/H/L se ries incorporates SPD(serial presence d etect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial P D data are program.

Part

HYMD564646Axx

Description

Unbuffered DDR SDRAM DIMM



Feature


www.DataSheet4U.com 64Mx64 bits Unbuffe red DDR SDRAM DIMM HYMD564646A(L)8-M/K /H/L DESCRIPTION Preliminary Hynix HYM D564646A(L)8-M/K/H/L series is unbuffer ed 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules(DIMMs ) which are organized as 64Mx64 high-sp eed memory arrays. Hynix HYMD564646A(L) 8-M/ K/H/L series consists of eight 64M x8 DDR SDRAM in 40.
Manufacture

Hynix

Datasheet
Download HYMD564646Axx Datasheet




 HYMD564646Axx
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DESCRIPTION
64Mx64 bits
Unbuffered DDR SDRAM DIMM
HYMD564646A(L)8-M/K/H/L
Preliminary
Hynix HYMD564646A(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules(DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix HYMD564646A(L)8-M/
K/H/L series consists of eight 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy sub-
strate.Hynix HYMD564646A(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor
of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD564646A(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD564646(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 512MB (64M x 64) Unbuffered DDR DIMM based on • Data inputs on DQS centers when write (centered
64Mx8 DDR SDRAM
DQ)
• JEDEC Standard 184-pin dual in-line memory mod- • Data strobes synchronized with output data for read
ule (DIMM)
and input data for write
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• 2.5V +/- 0.2V VDD and VDDQ Power supply
• Programmable CAS Latency 2 / 2.5 supported
• All inputs and outputs are compatible with SSTL_2
interface
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Fully differential clock operations (CK & /CK) with
100MHz / 133MHz
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• tRAS Lock-out function supported
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
ORDERING INFORMATION
Part No.
HYMD564646A(L)8-M
HYMD564646A(L)8-K
HYMD564646A(L)8-H
HYMD564646A(L)8-L
Power Supply
VDD=2.5V
VDDQ=2.5V
Clock Frequency
133MHz(DDR266 2-2-2)
133MHz(DDR266A)
133MHz (DDR266B)
100MHz (DDR200)
Interface
SSTL_2
Form Factor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
DataShee
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Feb. 2003
1
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 HYMD564646Axx
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PIN DESCRIPTION
Pin
CK0,/CK0,CK1,/CK1,CK2,/CK2
CS0
CKE0
/RAS, /CAS, /WE
A0 ~ A12
BA0, BA1
DQ0~DQ63
DQS0~DQS7
DM0~DM7
VDD
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
HYMD564646A(L)8-M/K/H/L
Pin
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
VDDID
DU
NC
Pin Description
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E2PROM Address Inputs
E2PROM Clock
E2PROM Data I/O
VDD Identification Flag
Do not Use
No Connection
PIN ASSIGNMENT
Pin Name Pin Name
1
VREF
32
A5
2
DQ0
33 DQ24
3 VSS 34 VSS
4
DQ1
35 DQ25
5 DQS0 36 DQS3
6
DQ2
37
A4
7 VDD 38 VDD
8
DQ3
39 DQ26
9 NC 40 DQ27
10 NC 41 A2
11 VSS 42 Vss
12 DQ8 43
A1
13 DQ9 44 CB0*
14 DQS1 45 CB1*
15 VDDQ 46
VDD
16 CK1 47 DQS8*
17 /CK1 48
A0
18 VSS 49 CB2*
19 DQ10 50
VSS
20 DQ11 51 CB3*
21 CKE0 52
BA1
22 VDDQ
Key
23 DQ16 53 DQ32
24 DQ17 54 VDDQ
25 DQS2 55 DQ33
26 VSS 56 DQS4
27 A9 57 DQ34
28 DQ18 58
VSS
29 A7 59 BA0
30 VDDQ 60 DQ35
31 DQ19 61 DQ40
Pin Name Pin Name
62 VDDQ 93
VSS
63 /WE 94 DQ4
64 DQ41 95
DQ5
65 /CAS
96 VDDQ
66 VSS 97 DM0
67 DQS5 98
DQ6
68 DQ42 99
DQ7
69 DQ43 100
VSS
70 VDD 101
NC
71 NC 102 NC
72 DaDQta48Sheet140U3 .comA13*
73 DQ49 104 VDDQ
74 VSS 105 DQ12
75 /CK2 106 DQ13
76 CK2 107 DM1
77 VDDQ 108
VDD
78 DQS6 109 DQ14
79 DQ50 110 DQ15
80 DQ51 111 CKE1
81 VSS 112 VDDQ
82 VDDID 113
BA2*
83 DQ56 114 DQ20
84 DQ57 115
A12
85 VDD 116 VSS
86 DQS7 117 DQ21
87 DQ58 118
A11
88
DQ59
119
DM2
89 VSS 120 VDD
90 WP 121 DQ22
91 SDA 122
A8
92 SCL 123 DQ23
Pin Name
124 VSS
125 A6
126 DQ28
127 DQ29
128 VDDQ
129 DM3
130 A3
131 DQ30
132 VSS
133 DQ31
134 CB4*
135 CB5*
136 VDDQ
137 CK0
138 /CK0
139 VSS
140 DM8*
141 A10
142 CB6*
143 VDDQ
144 CB7*
key
145 VSS
146 DQ36
147 DQ37
148 VDD
149 DM4
150 DQ38
151 DQ39
152 VSS
153 DQ44
Pin Name
154 /RAS
155 DQ45
156 VDDQ
157 /CS0
158 /CS1
159 DM5
160 VSS
161 DQ46
162 DQ47
163 NC
164 VDDQ
165 DQ52
166 DQ53
167 NC
168 VDD
169 DM6
170 DQ54
171 DQ55
172 VDDQ
173 NC
174 DQ60
175 DQ61
176 VSS
177 DM7
178 DQ62
179 DQ63
180 VDDQ
181 SA0
182 SA1
183 SA2
184 VDDSPD
DataShee
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.1/Feb. 2003
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 HYMD564646Axx
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HYMD564646A(L)8-M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS3
DM3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/CS0
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D0
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
/CS DQS
D1
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/CS DQS
D2
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DataSheet4UDM.c7om
/CS DQS
D3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D6
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D7
Serial PD
SCL
WP
A0 A1 A2
SA0 SA1 SA2
SDA
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
...... . ..= =
SPD
D0 – D7
D0 – D7
=
D0 – D7
Strap:see Note 4
*Clock Wiring
Clock Input
SDRAMs
*CK0,/CK0
*CK1,/CK1
*CK2,/CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per clock loading table/wiring diagrams
DataShee
BA0-BA1
A0 - A12
/RAS
/CAS
CKE0
/WE
BA0-BA1 : SDRAMs D0 – D7
A0 - A12 : SDRAMs D0 – D7
/RAS : SDRAMs D0 – D7
/CAS : SDRAMs D0 - D7
CKE : SDRAMs D0 – D7
/WE : SDRAMs D0 – D7
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown
3. DQ, DQS, DM/DQS resistors : 22Ohms+/-5%
4. VDDID strap connections
(for memory device VDD, VDDQ) :
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD= VDDQ
Rev. 0.1/Feb. 2003
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