DatasheetsPDF.com

ICX418ALL Dataheets PDF



Part Number ICX418ALL
Manufacturers Sony
Logo Sony
Description Diagonal 8mm (Type 1/2) CCD Image Sensor
Datasheet ICX418ALL DatasheetICX418ALL Datasheet (PDF)

ICX418ALL Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA B/W Video Cameras Description The ICX418ALL is an interline CCD solid-state image sensor suitable for EIA B/W video cameras with a diagonal 8mm (Type 1/2) system. Compared with the current product ICX038DLA, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically. This chip features a field period readout system and an electronic shutter with variable charge-storage time. This chip is compatible w.

  ICX418ALL   ICX418ALL


Document
ICX418ALL Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA B/W Video Cameras Description The ICX418ALL is an interline CCD solid-state image sensor suitable for EIA B/W video cameras with a diagonal 8mm (Type 1/2) system. Compared with the current product ICX038DLA, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically. This chip features a field period readout system and an electronic shutter with variable charge-storage time. This chip is compatible with the pins of the ICX038DLA and has the same drive conditions. 20 pin DIP (Cer-DIP) Pin 1 2 Features V • High sensitivity (+5.0dB compared with the ICX038DLA) • Low smear (–5.0dB compared with the ICX038DLA) • High D range (+2.0dB compared with the ICX038DLA) 3 • High S/N 40 H Pin 11 • High resolution and low dark current Optical black position • Excellent antiblooming characteristics (Top View) • Continuous variable-speed shutter • Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V) • Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V) • Horizontal register: 5V drive Device Structure • Interline CCD image sensor • Optical size: Diagonal 8mm (Type 1/2) • Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels • Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels • Chip size: 7.40mm (H) × 5.95mm (V) • Unit cell size: 8.4µm (H) × 9.8µm (V) • Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels • Number of dummy bits: Horizontal 22 Vertical 1 (even fields only) • Substrate material: Silicon 12 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01504A29 ICX418ALL Block Diagram and Pin Configuration (Top View) VOUT GND GND φSUB VDD Vφ1 Vφ2 Vφ3 Vφ4 VL 10 9 8 7 6 5 4 3 2 1 Vertical Register Note) Horizontal Register Note) 11 NC : Photo sensor 12 VDSUB 13 NC 14 GND 15 GND 16 RD 17 φRG 18 NC 19 Hφ1 20 Hφ2 Pin Description Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 Vφ4 Vφ3 Vφ2 φSUB GND Vφ1 VL GND VDD VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Substrate clock GND Vertical register transfer clock Protective transistor bias GND Output circuit supply voltage Signal output Pin No. Symbol 11 12 13 14 15 16 17 18 19 20 NC VDSUB NC GND GND RD φRG NC Hφ1 Hφ2 Horizontal register transfer clock Horizontal register transfer clock GND GND Reset drain bias Reset gate clock Substrate bias circuit supply voltage Description –2– ICX418ALL Absolute Maximum Ratings Item Substrate clock φSUB – GND Supply voltage Clock input voltage VDD, VRD, VDSUB, VOUT – GND VDD, VRD, VDSUB, VOUT – φSUB Vφ1, Vφ2, Vφ3, Vφ4 – GND Vφ1, Vφ2, Vφ3, Vφ4 – φSUB Ratings –0.3 to +50 –0.3 to +18 –55 to +10 –15 to +20 to +10 to +15 to +17 –17 to +17 –10 to +15 –55 to +10 –65 to +0.3 –0.3 to +30 –30 to +80 –10 to +60 Unit V V V V V V V V V V V V °C °C ∗1 Remarks Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins Hφ1, Hφ2 – Vφ4 φRG – GND φRG – φSUB VL – φSUB Pins other than GND and φSUB – VL Storage temperature Operating temperature ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –3– ICX418ALL Bias Conditions 1 [when used in substrate bias internal generation mode] Item Output circuit supply voltage Reset drain voltage Protective transistor bias Substrate bias circuit supply voltage Substrate clock Symbol VDD VRD VL VDSUB φSUB 14.55 Min. 14.55 14.55 Typ. 15.0 15.0 ∗1 15.0 ∗2 15.45 V Max. 15.45 15.45 Unit V V VRD = VDD Remarks ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. Bias Conditions 2 [when used in substrate bias external adjustment mode] Item Output circuit supply voltage Reset drain voltage Protective transistor bias Substrate bias circuit supply voltage Substrate voltage adjustment range Substrate voltage adjustment precision Symbol VDD VRD VL VDSUB VSUB ∆VSUB 6.0 –3 Min. 14.55 14.55 Typ. 15.0 15.0 ∗3 ∗4 14.0 +3 V % ∗5 ∗5 Max. 15.45 15.45 Unit V V VRD = VDD Remarks ∗3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗4 Connect to GND or leave open. ∗5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by .


ICX419AKL ICX418ALL ICX414AL


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)