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ICX412AQF Dataheets PDF



Part Number ICX412AQF
Manufacturers Sony
Logo Sony
Description Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor
Datasheet ICX412AQF DatasheetICX412AQF Datasheet (PDF)

ICX412AQF Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras Description The ICX412AQF is a diagonal 8.933mm (Type 1/1.8) interline CCD solid-state image sensor with a square pixel array and 3.24M effective pixels. Sensitivity, saturation signal, smear and frame rate have been improved compared to the ICX252AQF. This chip features an electronic shutter with variable charge-storage time. R, G, B primary color mosaic filters are used as the color fil.

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ICX412AQF Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras Description The ICX412AQF is a diagonal 8.933mm (Type 1/1.8) interline CCD solid-state image sensor with a square pixel array and 3.24M effective pixels. Sensitivity, saturation signal, smear and frame rate have been improved compared to the ICX252AQF. This chip features an electronic shutter with variable charge-storage time. R, G, B primary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, etc. 20 pin SOP (Plastic) Pin 1 Features • Supports frame readout • High horizontal and vertical resolution • Supports high frame rate readout mode: 30 frames/s, AF1 mode: 60 frames/s, 50 frames/s, AF2 mode: 120 frames/s, 100 frames/s • Square pixel • Horizontal drive frequency: 22.5MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • R, G, B primary color mosaic filters on chip • High sensitivity, low dark current • Continuous variable-speed shutter • Excellent anti-blooming characteristics • Exit pupil distance recommended range –20 to –100mm • 20-pin high-precision plastic package 2 V 8 4 Pin 11 H 48 Optical black position (Top View) Device Structure • Interline CCD image sensor • Total number of pixels: 2140 (H) × 1560 (V) approx. 3.34M pixels • Number of effective pixels: 2088 (H) × 1550 (V) approx. 3.24M pixels • Number of active pixels: 2080 (H) × 1542 (V) approx. 3.21M pixels diagonal 8.933mm • Number of recommended recording pixels: 2048 (H) × 1536 (V) approx. 3.15M pixels diagonal 8.832mm aspect ratio 4:3 • Chip size: 8.10mm (H) × 6.64mm (V) • Unit cell size: 3.45µm (H) × 3.45µm (V) • Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels • Number of dummy bits: Horizontal 28 Vertical 1 (even fields only) • Substrate material: Silicon ∗ Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (HoleAccumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony Corporation. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01657-PS ICX412AQF Block Diagram and Pin Configuration (Top View) TEST TEST VOUT GND Vφ1B Vφ1A Vφ3B Vφ3A 2 B Gr B Gr B Gr Note) Vφ2 10 9 8 7 6 5 4 3 Gb B Gr B Gr B Gr Gb R Gb R Gb R Vertical register R Gb R Gb R Horizontal register Note) : Photo sensor 11 12 13 14 15 16 17 18 19 Hφ2 Hφ1 VL Hφ1 φRG VDD Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol Vφ4 Vφ3A Vφ3B Vφ2 Vφ1A Vφ1B TEST TEST GND VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Test pin∗1 Test pin∗1 GND Signal output Pin No. 11 12 13 14 15 16 17 18 19 20 Symbol VDD φRG Hφ2 Hφ1 GND φSUB CSUB VL Hφ1 Hφ2 Description Supply voltage Reset gate clock Horizontal register transfer clock Horizontal register transfer clock GND Substrate clock Substrate bias∗2 Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock ∗1 Leave this pin open ∗2 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. φSUB CSUB GND –2– Hφ2 Vφ4 1 20 ICX412AQF Absolute Maximum Ratings Item VDD, VOUT, φRG – φSUB Vφ1A, Vφ1B, Vφ3A, Vφ3B – φSUB Against φSUB Vφ2, Vφ4, VL – φSUB Hφ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND Against φGND Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 – GND Hφ1, Hφ2 – GND Against φVL Vφ1A, Vφ1B, Vφ3A, Vφ3B – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Between input clock pins H φ1 – H φ2 Hφ1, Hφ2 – Vφ4 Ratings –40 to +12 –50 to +15 –50 to +0.3 –40 to +0.3 –25 to –0.3 to +22 –10 to +18 –10 to +6.5 –0.3 to +28 –0.3 to +15 to +15 –6.5 to +6.5 –10 to +16 –30 to +80 –10 to +60 –10 to +75 Unit V V V V V V V V V V V V V °C °C °C ∗1 Remarks Storage temperature Guaranteed temperature of performance Operating temperature ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. –3– ICX412AQF Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL φSUB φRG Min. 14.55 Typ. 15.0 ∗1 ∗2 ∗2 Max. 15.45 Unit V Remarks .


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