BCD Counter. CD4553 Datasheet

CD4553 Counter. Datasheet pdf. Equivalent

Part CD4553
Description (MC14553B) 3 Digit BCD Counter
Feature MC14553B 3-Digit BCD Counter The MC14553B 3–digit BCD counter consists of 3 negative edge triggered .
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Datasheet
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CD4553
MC14553B
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
–0.5 to +18.0
–0.5 to VDD + 0.5
Unit
V
V
Iin Input Current
(DC or Transient) per Pin
±10 mA
Iout Output Current
(DC or Transient) per Pin
+20 mA
PD Power Dissipation,
per Package (Note 2.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
–55 to +125
–65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14553BCP
AWLYYWW
1
16
SOIC–16
DW SUFFIX
CASE 751G
14553B
AWLYYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14553BCP
MC14553BDW
PDIP–16
SOIC–16
25/Rail
47/Rail
© Semiconductor Components Industries, LLC, 2001
February, 2001 – Rev. 5
1
Publication Order Number:
MC14553B/D



CD4553
MC14553B
43
CIA CIB Q0
9
12 CLOCK
Q1 7
10 LE
Q2 6
Q3 5
11 DIS
O.F. 14
DS1 2
13 MR
DS2 1
DS3 15
VDD = PIN 16
VSS = PIN 8
Figure 1. Block Diagram
TRUTH TABLE
Inputs
Master
Reset
Clock Disable
LE
Outputs
0
00
No Change
0
00
Advance
0X1X
No Change
01
0 Advance
01
0 No Change
0 0XX
No Change
0 XX
Latched
0 XX 1
Latched
1 X X 0 Q0 = Q1 = Q2 = Q3 = 0
X = Don’t Care
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