PAL/SECAM/NTSC BASE 1H DELAY SYSTEM
TA8772AN
TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA8772AN
PAL / SECAM / NTSC BASE BAND 1H DELAY SYS...
Description
TA8772AN
TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA8772AN
PAL / SECAM / NTSC BASE BAND 1H DELAY SYSTEM FOR COLOR TV OR VCR
The TA8772AN has two chips, a bipolar chip and a CCD chip, in a package. CCD chip consist of two delaylines which operate to delay R-Y and B-Y signal. Bipolar chip operate to control the signals which is processed by CCD stage.
FEATURES
Bipolar stage
l AGC circuit l L.P.F. l DC clamp circuit
l Mode SW l 225fH VCO circuit
(For correcting output level)
(For reducing CCD clock)
(For reducing the difference of DC l vel between delay signal and direct ignal.)
Weight: 1.99g (Typ.)
(For control output signal by PAL, NTSC or SECAM ident)
(For making CCD clock)
CCD stage
l CCD drive circuit l Sample & Hold circuit l Input bias circuit l Synctip clamp circuit (This device’s dynamic range bear no relation to change of APL on adopt this circuit) l Delay time of 1H consist of supply 225fH clock.
TOTAL
l This device can operate by the smallest external parts because of include CCD drive circuit, bias generator circuit and output amplifier for support CCD circuit.
1 2002-01-17
BLOCK DIAGRAM
TA8772AN
2 2002-01-17
TERMINAL FUNCTION
PIN No.
PIN NAME
FUNCTION
1
R-Y Clamp Det.
This is a terminal for detecting DC clamp level of R-Y signal.
28
B-Y Clamp Det.
This is a terminal for detecting DC clamp level of R-Y signal.
INTERFACE CIRCUIT
2 R-Y to CCD
This is output terminal of R-Y signal.
This terminal connects to pin 15 of C...
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