5V Applications. AN240 Datasheet
Interfacing 3V and 5V applications
Authors: Tinus van de Wouw (Nijmegen) / Todd Andersen (Albuquerque)
1.0 THE NEED FOR INTERFACING BETWEEN 3V
AND 5V SYSTEMS
Many reasons exist to introduce 3V1 systems, notably the lower
power consumption for mobile applications and the introduction of
parts that use technologies with such fine geometries that 5V is
simply not allowed any more.
The introduction of the 3V standard as supply voltage has resulted
in many design activities for digital systems. Very often, however,
there is a gradual transition from 5V to 3V, since not always are all
required components available, or the system is rather complex so
that 3V is introduced in part of a system. As an example, customers
wish to use an existing and proven CPU, while a new, more complex
ASIC with added features can only be made with 3V. Or vice versa!
With the introduction of new standards such as 2.2-2.7V or even
1.7V we expect that interfacing between systems that use different
supply voltages will be an actual issue for many years to come. This
application note specifically addresses the interfacing between 3V
and 5V systems, but the results can be applied for interfacing
between other voltage levels as well.
We will discuss how one can ensure reliable information exchange
and how to prevent current flow between both supply voltages when
interfacing logic with memories, ASICs, PLDs and microprocessors
at different supply voltages.
Figure 1. Switching Levels
One issue remains: a 3V system driving a 5V one that has CMOS
input levels. This cannot be reliably done by standard 3V logic
families, even when using pull-up resistors, simply because under
worst case conditions, the output voltage is not high enough to
guarantee that the signal will be seen as a logical “1”. Philips
Semiconductors developed special dual VCC levelshifters to address
that situation (see Section 6.0).
2.0 LEVEL SHIFTING - INPUT AND OUTPUT
We obviously want a reliable signal transfer from the 5V system to
the 3V system and vice versa. This implies that the output voltages
should be such that the input levels are exceeded.
2.1 TTL and CMOS Switching Levels
As a reminder, digital circuits have input levels defined: one voltage
(VIL) below which the circuit certainly sees it as a logical “0” and
another voltage (VIH) above which the input is guaranteed “1”.
Digital circuits normally come in two versions:
• TTL levels: VIL = 0.8V, VIH = 2.0V
• CMOS levels: VIL = 0.3 < VCC, VIH = 0.7 < VCC.
For systems with VCC = 5.0 " 0.5V this practically means:
VIL = 1.35V, VIH = 3.85V.
2.2 Level Shifting from 5V to 3V
All 5V families have an output voltage swing that is large enough to
drive 3V reliably. As described in Section 4.0, outputs may be as
high as 3.5V for many “TTL” output stages, to the full 5V for many
CMOS outputs. Therefore, as far as switching levels are concerned,
there are no problems in interfacing from 5V to a 3V system.
2.3 Level Shifting from 3V to 5V
All 3V logic families deliver practically the full output voltage swing of
3V, so they can drive TTL switching levels without problems (see
3.0 INPUT STRUCTURES OF DIGITAL CIRCUITS
Before discussing further issues on 3-5V interfacing we should start
by investigating the inputs of digital circuits in order to understand
what care one should take to prevent problems.
3.1 ESD Input Protection Circuits
Virtually all inputs of a digital circuit contain an ESD protection circuit
that prevents damage against electrostatic discharge. This circuit is
present between the physical input pin and the active circuit. Two
popular schemes are given in Fig. 2.
Figure 2. ESD Protection Circuits
The classic CMOS scheme as shown left provides protection
against negative zaps by the diodes to ground. Positive zaps are
clamped by the diode to VCC. The real disadvantage is that the
maximum input voltage of such a circuit is limited to VCC + 0.5V. For
a VCC of 3V the allowed input voltage is too low for direct interfacing
to most 5V systems.
1. We use the expression “3V” when a supply voltage is used between 2.7 and 3.6V.
1995 Sep 15
Interfacing 3V and 5V applications
Modern low voltage circuits use a double transistor circuit as shown
right that was pioneered in our ABT families. Two transistors (Bipolar
or MOS) act as fast Zener diodes protecting against positive zaps.
Now, there is no diode to VCC and the maximum input voltage is not
limited by VCC.
Typically, such circuits have a breakdown voltage between 7 and
10V, easily allowing input voltages from any 5V system.
LV is the only family that employs a classic protection circuit, all
other Philips Semiconductors low voltage logic families have the
dual transistor protection circuit.
3.2 Bus Hold Circuits
ALVC, LVC16 and LVT families use bus hold circuits as shown in
Fig. 3. A bus hold circuit holds the input at the most recent value
when the input is left floating by using a small MOS transistor as
pull-up or pull-down device.
One important point to note is that there is an intrinsic diode
between the source and the drain of the upper PMOS as shown in
Fig. 4. This may cause a current to flow from the output to VCC
when the voltage on the output pin is lifted higher than one diode
voltage above VCC.
Figure 3. Bus hold circuits
A bus hold circuit for CMOS as shown left has also a diode between
the input and VCC which is formed by the intrinsic diode between the
source and drain of the upper PMOS. This means that for ALVC and
LVC16 the input voltage is limited to VCC + 0.5V.
A different bus hold circuit is used in LVT parts as shown right due to
the versatility of the QUBiC process which allows the use of a series
Schottky diode so that there is no current path to VCC in the bus
hold circuit used for LVT.
4.0 OUTPUT STAGES OF DIGITAL CIRCUITS
Output structures of digital circuits (see Figs. 4 and 8) determine the
output voltage swing. Circuits may swing between GND and VCC or
the swing may be limited by voltages developed internally.
Also, output structures determine the behavior when the output pin
is taken above VCC, which may be the case when two outputs are
tied together on a common bus.
4.1 Bipolar Output Stage
A typical bipolar output structure does not have the full output
voltage swing. When a 5V output is active HIGH, the output voltage
is limited to VCC – 2 < VBE ( = approx. 3.6V). Therefore, quite often,
interfacing with 3V systems works without currents flowing from the
5V supply into the 3V supply, or the current is so low that there is no
4.2 CMOS output stage
The output for a typical CMOS part swings fully between GND and
Figure 4. Typical digital output structures
4.3 Other MOS Output Structures
Some other MOS output stages such as many SRAM and DRAM
circuits may have a circuit that shows a behavior similar to a bipolar
output stage. An example is given Fig. 4: the upper NMOS limits the
output voltage to VCC – VTH ( = approx. 3.5V). Such a circuit often
works fine when driving 3V systems.
4.4 Open Collector/Open Drain
Some parts have an “Open Collector” or “Open Drain” output stage
and there is no internal circuit to pull the output high. Normally a
pull-up resistor connects the output to a voltage that can be higher
than VCC. Obviously such parts allow easy interfacing, but for speed
reasons the pull-up resistor often needs to be relatively small, so the
use of pull-up resistors increases power losses.
4.5 The BiCMOS Output
A BiCMOS output combines the advantages of bipolar (i.e. high
output drive, low noise) and CMOS (full output voltage swing, low
standby current). The output stage of Philips Semiconductors
BiCMOS parts has some specific features that will be discussed in
1995 Sep 15