PLL500-17

PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) FEATURES VCXO output for the 17MHz to 36MHz range Low phase noise (-130 dBc @ 10kHz offset at 35.328MHz). CMOS output with OE tri-state control. 17 to 36MHz fundamental crystal input. Integrated high linearity variable capacitors. 12mA drive capability at TTL output. +/- 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. 2.5 to 3.3V operation. Available in 8-Pin SOIC, 6-pin SOT23 packages, or DIE. BLOCK DIAGRAM PIN CONFIGURATION XIN VDD* VIN GND 1 2 3 4 8 7 6 5 XOUT OE^ VDD* CLK ^: Denotes internal Pull-up *: Only one VDD pin needs to be connected PLL500-17 DESCRIPTION The PLL500-17 is a low cost, high performance and low phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 17 to 36MHz (fundamental resonant mode). OUT GND CLK 1 2 3 6 5 4 XIN VDD VIN PLL500-17 FREQUENCY RANGE MULTIPLIER No PLL FREQUENCY 17 – 36 MHz OUTPUT BUFFER CMOS 8-pin SOIC 6-pin SOT XIN XOUT XTAL OSC VARICAP OE VCON 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 1 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) DIE PAD LAYOUT 32 mil (812,986) DIE SPECIFICATIONS Name Value 8 1 XIN XOUT OE^ 7 39 mil 2 VDD VDD 6 ...