DatasheetsPDF.com

PLL1707 Dataheets PDF



Part Number PLL1707
Manufacturers Burr-Brown
Logo Burr-Brown
Description (PLL1708) 3.3 V DUAL PLL MULTICLOCK GENERATOR
Datasheet PLL1707 DatasheetPLL1707 Datasheet (PDF)

PLL1707 PLL1708 SLES065 – DECEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL1708): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS, 384 fS, 256 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 16, 22.05, 24, 32,.

  PLL1707   PLL1707



Document
PLL1707 PLL1708 SLES065 – DECEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL1708): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS, 384 fS, 256 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitter: 50 ps (Typical) Multiple Sampling Frequencies (PLL1707): – fS = 32, 44.1, 48, 64, 88.2, 96 kHz Multiple Sampling Frequencies (PLL1708): – fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz 3.3-V Single Power Supply PLL1707: Parallel Control PLL1708: Serial Control Package: 20-Pin SSOP (150 mil), Lead-Free Product APPLICATIONS D D D D D D D HDD + DVD Recorders DVD Recorders HDD Recorders DVD Players DVD Add-On Cards for Multimedia PCs Digital HDTV Systems Set-Top Boxes D DESCRIPTION The PLL1707† and PLL1708† are low cost, phase-locked loop (PLL) multiclock generators. The PLL1707 and PLL1708 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1707 can be controlled by sampling frequency-control pins and those of the PLL1708 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1707 and PLL1708 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD recorders, HDD recorders, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. D D D D D D D This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002, Texas Instruments Incorporated P.


PLL200 PLL1707 PLL1700


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)