MT48LC1M16A1

16Mb: x16 IT SDRAM SYNCHRONOUS DRAM FEATURES PC100 functionality Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge 1 Meg x 16 - 512K x 16 x 2 banks architecture with 11 row, 8 column addresses per bank Programmable burst lengths: 1, 2, 4, 8 or full page Auto Precharge Mode, includes CONCURRENT AUTO PRECHARGE Self Refresh and Adaptable Auto Refresh Modes - 32ms, 2,048-cycle refresh or - 64ms, 2,048-cycle refresh or - 64ms, 4,096-cycle refresh LVTTL-compatible inputs and outputs Single +3.3V ±0.3V power supply Supports CAS latency of 1, 2 and 3 Industrial temperature range: -40°C to +85°C MT48LC1M16A1 SIT - 512K x 16 x 2 banks INDUSTRIAL TEMPERATURE For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/sdramds.html PIN ASSIGNMENT (Top View) 50-Pin TSOP VDD DQ0 DQ1 VssQ DQ2 DQ3 VDDQ DQ4 DQ5 VssQ DQ6 DQ7 VDDQ DQML WE# CAS# RAS# CS# BA A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Vss DQ15 DQ14 VssQ DQ13 DQ12 VDDQ DQ11 DQ10 VssQ DQ9 DQ8 VDDQ NC DQMH CLK CKE NC A9 A8 A7 A6 A5 A4 Vss OPTIONS Configuration 1 Meg x 16 (512K x 16 x 2 banks) Plastic Package - OCPL* 50-pin TSOP (400 mil) Timing (Cycle Time) 6ns (166 MHz) 7ns (143 MHz) 8ns (125 MHz) MARKING...