MC74HC4514

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1-of-16 Decoder/Demultiplexer with Address Latch High–Performance Silicon–Gate CMOS The MC74HC4514 is identical in pinout to the MC14514B metal–gate CMOS device. The device inputs are compatible with standard CMOS outputs, with pullup resistors; they are compatible with LSTTL outputs. This device consists of a 4–bit storage latch with a Latch Enable and Chip Select input. When a low signal is applied to the Latch Enable input, the Address is stored, and decoded. When the Chip Select input is high, all sixteen outputs are forced to a low level. The Chip Select input is provided to facilitate the chip–select, demultiplexing, and cascading functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and then by using the Chip Select as a data input. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 268 FETs or 67 Equivalent Gates 24 MC74HC4514 N SUFFIX PLASTIC PACKAGE CASE 724–03 1 24 1 DW SUFFIX SOIC PACKAGE CASE 751E–04 ORDERING INFORMATION MC74HCXXXXN MC74HCXXXXDW Plastic SOIC PIN ASSIGNMENT LATCH ENABLE A0 A1 Y7 Y6 Y5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC CHIP SELECT A3 A2 Y10 Y11 Y8 Y9 Y14 Y15 Y12 Y...