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MC74HC132A Dataheets PDF



Part Number MC74HC132A
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Quad 2-Input NAND Gate
Datasheet MC74HC132A DatasheetMC74HC132A Datasheet (PDF)

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High−Performance Silicon−Gate CMOS MC74HC132A The MC74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhance noise immunity or to square up slowly changing waveforms. Features • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 .

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Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High−Performance Silicon−Gate CMOS MC74HC132A The MC74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhance noise immunity or to square up slowly changing waveforms. Features • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements as Defined by JEDEC Standard No. 7A • Chip Complexity: 72 FETs or 18 Equivalent Gates • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant A1 1 B1 2 Y1 3 A2 4 B2 5 Y2 6 GND 7 14 VCC 13 B4 12 A4 11 Y4 10 B3 9 A3 8 Y3 Figure 1. Pin Assignment DATA SHEET www.onsemi.com 14 1 MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 1 HC132AG AWLYWW 14 1 TSSOP−14 DT SUFFIX CASE 948G 14 HC 132A ALYWG G 1 A L, WL Y, YY W, WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs A B L L L H H L H H Output Y H H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2013 1 December, 2021 − Rev. 17 Publication Order Number: MC74HC132A/D A1 1 B1 2 A2 4 B2 5 A3 9 B3 10 A4 12 B4 13 MC74HC132A 3 Y1 6 Y2 Y = AB 8 Y3 11 Y4 PIN 14 = VCC PIN 7 = GND Figure 2. Logic Diagram ORDERING INFORMATION Device Package Shipping† MC74HC132ADG SOIC−14 (Pb−Free) 55 Units / Rail MC74HC132ADR2G SOIC−14 (Pb−Free) 2500 / Tape & Reel MC74HC132ADTG TSSOP−14 (Pb−Free) 96 Units / Rail MC74HC132ADTR2G TSSOP−14 (Pb−Free) 2500 / Tape & Reel NLV74HC132ADG* SOIC−14 (Pb−Free) 55 Units / Rail NLV74HC132ADR2G* SOIC−14 (Pb−Free) 2500 / Tape & Reel NLV74HC132ADTG* TSSOP−14 (Pb−Free) 96 Units / Rail NLV74HC132ADTR2G* TSSOP−14 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable www.onsemi.com 2 MC74HC132A MAXIMUM RATINGS Symbol Parameter Value Unit VCC VIN VOUT IIK IOK IOUT ICC IGND TSTG TL TJ qJA Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance 14−SOIC 14−TSSOP *0.5 to +7.0 *0.5 to VCC+0.5 *0.5 to VCC+0.5 $20 $20 $25 $75 $75 −65 to +150 260 +150 125 170 V V V mA mA mA mA mA _C _C _C _C/W PD Power Dissipation in Still Air at 85_C SOIC 500 mW TSSOP 450 MSL Moisture Sensitivity Level 1 FR VESD Flammability Rating ESD Withstand Voltage Oxygen Index: 30% − 35% UL 94 V0 @ 0.125 in Human Body Model (Note 1) u2000 V Machine Model (Note 2) u100 Charged Device Model (Note 3) u500 ILatch−Up Latch−Up Performance Above VCC and Below GND at 85_C (Note 4) $300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to JESD22−C101−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VIN, VOUT ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 3) Min 2.0 0 *55 − Max Unit 6.0 V VCC V )125 _C No Limit ns (Note 5) 5. When VIN X 0.5 VCC, ICC >> quiescent current. 6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter VT+max Maximum Positive−Go.


MC74HC132A MC74HC132A MN155201


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