MT5C1001

Austin Semiconductor, Inc. 1M x 1 SRAM SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS SMD 5962-92316 MIL-STD-883 MT5C1001 Limited Availability PIN ASSIGNMENT (Top View) SRAM 28-Pin DIP (C) (400 MIL) A10 A11 A12 A13 A14 A15 NC A16 A17 A18 A19 Q WE\ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc A9 A8 A7 A6 A5 A4 NC A3 A2 A1 A0 D CE\ 32-Pin LCC (EC) 32-Pin SOJ (DCJ) A10 A11 A12 NC A13 A14 A15 NC A16 A17 A18 A19 NC Q WE\ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc NC A9 A8 A7 A6 A5 A4 A3 NC A2 NC A1 A0 D CE\ FEATURES High Speed: 20, 25, 35, and 45 Battery Backup: 2V data retention Low power standby Single +5V (+10%) Power Supply Easy memory expansion with CE\ and OE\ options. All inputs and outputs are TTL compatible Three-state output 32-Pin Flat Pack (F) OPTIONS Timing 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access Package(s) Ceramic DIP (400 mil) Ceramic LCC Ceramic Flatpack Ceramic SOJ MARKING -20 -25 -35 -45 -55* -70* A10 A11 A12 NC A13 A14 A15 NC A16 A17 A18 A19 NC Q WE\ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc NC A9 A8 A7 A6 A5 A4 A3 NC A2 NC A1 A0 D CE\ C EC F DCJ No. 109 No. 207 No. 303 No. 501 GENERAL DESCRIPTION The MT5C1001 employs low power, high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing strobes ...