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IDT5V927 Dataheets PDF



Part Number IDT5V927
Manufacturers IDT
Logo IDT
Description Quad Output Clock Generator
Datasheet IDT5V927 DatasheetIDT5V927 Datasheet (PDF)

IDT5V927 QUAD OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE QUAD OUTPUT CLOCK GENERATOR IDT5V927 FEATURES: • • • • • • • • 3V to 3.6V operating voltage 50MHz to 160MHz output frequency range Input from fundamental crystal oscillator or external source Internal PLL feedback (loading feedback output relative to other outputs, adjusts propagation delay between REF inputs and outputs) Select inputs (S[1:0]) for FB divide selection (multiply ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8) Low j.

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IDT5V927 QUAD OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE QUAD OUTPUT CLOCK GENERATOR IDT5V927 FEATURES: • • • • • • • • 3V to 3.6V operating voltage 50MHz to 160MHz output frequency range Input from fundamental crystal oscillator or external source Internal PLL feedback (loading feedback output relative to other outputs, adjusts propagation delay between REF inputs and outputs) Select inputs (S[1:0]) for FB divide selection (multiply ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8) Low jitter PLL bypass for testing and power-down control (S1 = H, S0 = H, powers part down <500µ A) Available in TSSOP package The IDT5V927 is a low-cost, low skew, low jitter, and high-performance clock synthesizer. It has been specially designed to interface with Gigabit Ethernet (125MHz), Fibre Channel (106.25MHz), and OC-3 (155.52MHz) applications. It can be programmed to provide output frequencies ranging from 50MHz to 160MHz, with input frequencies ranging from 6.25MHz to 80MHz. The IDT5V927 includes an internal RC filter that provides excellent jitter characteristics and eliminates the need for external components. When using the optional crystal input, the chip accepts a 10 - 40MHz fundamental mode crystal with a maximum equivalent series resistance of 50Ω. DESCRIPTION: APPLICATIONS: • • • • • • Gigabit ethernet Router Network switches SAN Instrumentation Fibre channel FUNCTIONAL BLOCK DIAGRAM OE VCO DIVIDE 1/N REF PHASE DETECTOR CHARGE PUM P LOO P FILTER VCO Q0 Q1 0 Q2 1 Q3 X2 CRYSTAL O SCILLATO R X1 SELECT M O DE S1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. S0 INDUSTRIAL TEMPERATURE RANGE 1 c 2003 Integrated Device Technology, Inc. FEBRUARY 2003 DSC 5853/6 IDT5V927 QUAD OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION REF X1 X2 VDD Q0 GND Q1 VDDQ 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 S0 S1 OE GND Q3 GND Q2 VDDQ ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD/VDDQ VI IO TSTG TJ Description Supply Voltage to Ground Input Voltage Output Current Storage Temperature Junction Temperature Max. – 0.5 to +4.6 – 0.5 to +4.6 ±50 – 65 to +150 150 Unit V V mA °C °C NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PIN DESCRIPTION Pin Name Type S[1:0] I I OE Description Three level divider/mode select pins. Float to MID. Output enable bar. OE has a pull-down. Output Q[1:3] tristated when HIGH. Output Q0 remains running when in PLL mode and tri-states when in TEST mode. Crystal oscillator input. Connect to GND if oscillator not required. Crystal oscillator output. Leave unconnected for clock input. Input clock. Connect to X2 if crystal oscillator is used. Output at N*REF frequency Output at N*REF internally connected for PLL feedback Power supply for the device outputs. Connect to VDD on PCB. Power supply for the device core and inputs. Connect to VDD on PCB. GND PWR Ground supply TSSOP TOP VIEW X1 X2 REF Q[1:3] Q0 VDDQ VDD I I I O O PWR PWR CRYSTAL SPECIFICATION The crystal oscillators should be fundamental mode quartz crystals: overtone crystals are not suitable. Crystal frequency should be specified for parallel resonance with 50Ω maximum equivalent series resonance. Crystal tuning capacitors should be connected from X2/REF to GND and from X1 to GND. DIVIDE SELECTION TABLE(1) S1 L L L M M M H H H S0 L M H L M H L M H Divide-by-N Value 2 3 4 4.25 5 6 6.25 8 TEST Mode PLL PLL PLL PLL PLL PLL PLL PLL TEST (2) NOTES: 1. H = HIGH M = MEDIUM L = LOW 2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down. 2 IDT5V927 QUAD OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE COMMON OUTPUT FREQUENCY EXAMPLES (MHz) Output Input FB Divide Selection S[1:0] Output Input FB Divide Selection S[1:0] 50 25 LL 106.25 17 HL 60 10 MH 106.25 25 ML 64 16 LH 120 15 HM 72 12 MH 125 20 HL 75 25 LM 125 25 MM 80 10 HM 125 62.5 LL 90 15 MH 150 25 MH 100 20 MM 155.52 19.44 HM OPERATING CONDITIONS Symbol VDD/VDDQ TA CL CIN Parameter Power Supply Voltage Operating Temperature Output Load Capacitance Input Capacitance, OE, F = 1MHz, VIN = 0V, TA = 25°C Min. 3 - 40 — — Typ. 3.3 25 — 5 Max. 3.6 +85 15 7 Unit V °C pF pF DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VDD/VDDQ = 3.3V ±0.3V Symbol VIL VIH VIHH VIMM VILL IIN I3 IIH VOL VOH Parameter Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current (REF input only) 3-Level Input DC Current, S[1:0] Input HIGH Current Output LOW Voltage Output HIGH Voltag.


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