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HYMP512R72x Dataheets PDF



Part Number HYMP512R72x
Manufacturers Hynix
Logo Hynix
Description 128M x 72 Bits DDR2 SDRAM Registered DIMM
Datasheet HYMP512R72x DatasheetHYMP512R72x Datasheet (PDF)

128Mx72 bits DDR2 SDRAM Registered DIMM HYMP512R72(L)4 Revision History No. 0.1 History 1) Defined Target Spec. 1) Added Pin Capacitance Spec. & IDD Spec. 2) Corrected SPD typo(byte #22,#42) Corrected Pin assignment table Draft Date Feb. 2004 Apr. 2004 July 2004 Remark 0.2 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / July 2.

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128Mx72 bits DDR2 SDRAM Registered DIMM HYMP512R72(L)4 Revision History No. 0.1 History 1) Defined Target Spec. 1) Added Pin Capacitance Spec. & IDD Spec. 2) Corrected SPD typo(byte #22,#42) Corrected Pin assignment table Draft Date Feb. 2004 Apr. 2004 July 2004 Remark 0.2 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / July 2004 1 128Mx72 bits DDR2 SDRAM Registered DIMM HYMP512R72(L)4 DESCRIPTION Hynix HYMP512R72(L)4 series is registered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMP512R72(L)4 series consists of eighteen 128Mx4 DDR2 SDRAMs in 60-Lead FBGA chipsize packages. Hynix HYMP512R72(L)4 series provide a high performance 8-byte interface in 133.35mm width form factor of industry stanard. It is suitable for easy interchange and addition. Hynix HYMP512R72(L)4 series is designed for high speed of up to 333MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMP512R72(L)4 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES • • 1GB (128M x 72) Registered DDR2 DIMM based on 128Mx4 DDR2 SDRAMs JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply JEDEC Standard 240-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability All inputs and outputs are compatible with SSTL_1.8 interface OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) • • • • • • Fully differential clock operations (CK & /CK) Programmable CAS Latency 3 / 4 /5 supported Programmable Burst Length 4 / 8 with both sequential and interleave mode All inputs and outputs SSTL_1.8 compatible Auto refresh and self refresh supported 7.8us refresh period at Lower than TCASE 85℃, 3.9us( 85 ℃ < TCASE ≤ 95℃) • • Serial Presence Detect(SPD) with EEPROM DDR2 SDRAM Package: 60ball FBGA • • • • ORDERING INFORMATION Type PC2-3200 (DDR2-400) HYMP512R72(L)4-E3 HYMP512R72(L)4-C5 PC2-4300 (DDR2-533) HYMP512R72(L)4-C4 HYMP512R72(L)4-Y6 PC2-5300 (DDR2-667) HYMP512R72(L)4-Y5 5-5-5 one rank 1GB Reg. DIMM 3-3-3 5-5-5 4-4-4 6-6-6 240pin Registered DIMM 133.35 mm x 30,00 mm (MO-237) Part No. HYMP512R72(L)4-E4 Description CL-tRCD-tRP 4-4-4 Form Factor This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / July 2004 2 HYMP512R72(L)4 Input/Output Functional Description Symbol CK0~CK1 Type IN Polarity Positive Edge Negative Edge Active High Pin Description Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CK0~CK1 IN Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CKE0~CKE1 IN Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 On-Die Termination signals. When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the command being entered. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. S0~S1 IN Active Low ODT0~ODT1 RAS, CAS, WE Vref VDDQ BA0~BA1 IN IN Supply Supply IN Active High Active Low - Selects which DDR2 SDRAM internal bank of four is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA13) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling .


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