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CH7013B
Chrontel CHRONTEL CHRONTEL CHRONTEL
Digital PC to TV Encoder
1. FEATURES
• Universal digital interface accepts YCrCb (CCIR601 or 656) or RGB (15, 16 or 24-bit) video data in both non-interlaced and interlaced formats • True scale rendering engine supports underscan operations for various graphics resolutions • Enhanced text sharpness and adaptive flicker removal with up to 5-lines of filtering • Enhanced dot crawl control and area reduction • Fully programmable through serial port • Supports NTSC, NTSC-J, and PAL (B, D, G, H, I, M and N) TV formats • Provides Composite, S-Video and SCART outputs • Auto-detection of TV presence • Supports VBI pass-through • Programmable power management • 9-bit video DAC outputs • Complete Windows and DOS driver software • Offered in 48-pin LQFP
2. GENERAL DESCRIPTION
Chrontel’s CH7013B digital PC to TV encoder is a standalone integrated circuit providing a robust solution for TV output. It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts it directly into the NTSC or PAL TV format. This device integrates a digital NTSC/PAL encoder with a 9bit DAC interface, an adaptive flicker filter, and a high accuracy low-jitter phase locked loop to create outstanding quality video. Through its true scale scaling and deflickering engine, the CH7013B supports full vertical and horizontal underscan capability and operates in 5 different resolutions including 640x480 and 800x600. A universal digital interface along with full programmability make the CH7013B ideal for system-level PC solutions. All features are software programmable through a serial port to enable a complete PC solution using a TV as the primary display.
LINE MEMORY
YUV-RGB CONVERTER
RGB-YUV CONVERTER DIGITAL
D[15:0] PIXEL DATA
INPUT INTERFACE
TRUE SCALE SCALING & DEFLICKERING ENGINE
NTSC/PAL ENCODER & FILTERS
Y/R TRIPLE DAC C/G CVBS/B
SYSTEM CLOCK
RSET
SERIAL CONTROL
BLOCK
PLL
TIMING & SYNC GENERATOR
CLOCK
DATA
ADDR
XCLK
H
V
XI XO/FIN CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
201-0000-069
Rev. 1.2, 9/1/2004
1
CHRONTEL
3. PIN DESCRIPTIONS
3.1 Package Diagram
CH7013B
P-OUT
DGND
AGND
DVDD
XCLK
BCO
D[2]
D[1]
D[0]
48
47
46 45
44
43
42
41
40
39
38
D[3] D[4] D[5] D[6] DVDD D[7] D[8] DGND D[9] D[10] D[11] NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
37 36 35 34 33
XO/FIN XI AVDD DVDD ADDR DGND CLOCK DATA VDD RSET GND NC
NC
H
V
CHRONTEL CH7013B
32 31 30 29 28 27 26 25
16
17
18 19
20
21 22
CVBS GND
23
C
D[12]
D[13]
D[14]
D[15]
NC
CSYNC
DVDD
Figure 2: 48-PIN LQFP (7mm x 7mm)
2
DGND
Y
201-0000-069
24
Rev. 1.2,
9/1/2004
CHRONTEL
3.2 Pin Descriptions
Table 1. Pin Descriptions
48-Pin LQFP
17-14, 11-9, 7-6, 4-1, 48-46
CH7013B
Type
In
Symbol
D15-D0
Description
Digital Pixel Inputs These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed or 16-bit non-multiplexed formats, determined by the input mode setting (see Registers and Programming section). Inputs D0 - D7 are used when operating in 8bit multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode. Inputs D0 - D15 are used when operating in 16-bit mode. The data structure and timing sequence for each mode is described in the section on Digital Input Port. Pixel Clock Output The CH7013B, operating in master mode, provides a pixel data clocking signal to the VGA controller. This pin provides the pixel clock output signal (adjustable as X, 2X or 3X) to the VGA controller (see the section on Digital Video Interface and Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum. Pixel Clock Input To operate in a pure master mode, the P-OUT signal should be connected to the XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P-OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7013B accepts an external pixel clock input at this pin. The capacitive loading on this pin should be kept to a minimum. Vertical Sync Input/Output This pin accepts the vertical sync signal from the VGA controller, or outputs a vertical sync to the VGA controller. The capacitive loading on this pin should kept to a minimum. Horizontal Sync Input/Output This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal sync to the VGA controller. The capacitive loading on this pin should be kept to a minimum. Buffered Clock Output This pin provides a buffered output of the 14.31818 MHz crystal input frequency for other devices and remains active at all times (including power-down). The output can also be selected to be other frequencies (see Registers and Programming). Crystal Input A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock .