MN6155

For Communications Equipment MN6155 PLL LSI with Built-In Prescaler Overview The MN6155 is a CMOS LSI for a phase-locked loop (PLL) frequency synthesizer with serial data parameter input. It consists of a two-coefficient prescaler, variable frequency divider, phase comparator, and charge pump. It offers high-speed operation on a low power supply voltage (1.0 to 1.4 V) and low power consumption (1.65 mW for VDD=1.1 V, F IN= RIN =90 MHz). Other features include intermittent operation by the power save (PS) control signal and high-speed pull-in that rapidly corrects the phase differences occurring at the start of operation. It also offers two choices for the reference signal: selfexcited operation using the built-in inverter amplifier or use of an external, separately excited oscillator. Pin Assignment XIN XOUT FV VDD DOP VSS VCP FIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RIN RSL LC FR PS LE DATA CLK (TOP VIEW) SSOP016-P-0225 Features Low power supply voltage: VDD=1.0 to 1.4V Low power consumption: 1.65mW(VDD=1.10V, FIN =90MHz, RIN =90MHz) High-speed operation: FIN=90MHz, R IN=90MHz (VDD=1.1V) Frequency dividing ratios in reference frequency dividing stage 6 to 131,070 for RSL at "H" level (even number setting is available) 272 to 131,071 for RSL at "L" level Frequency dividing ratios for comparator stage: 272 to 262,143 Power supply pin for built-in charge pump VCP=2.5 to 3.2V Output monitor pins for both comparator and reference frequency dividing stages MN6155 Block...