MN6153UC

For Communications Equipment MN6153UC PLL LSI with Built-In Prescaler Overview The MN6153UC is a CMOS LSI for a phase-locked loop (PLL) frequency synthesizer with serial data input. It consists of a two-coefficient prescaler, variable frequency divider, phase comparator, and charge pump. It offers high-speed operation on a low power supply voltage (1.0 to 1.4 V) and low power consumption (0.5 mW for VDD=1.03 V, F IN= 60 MHz). Other features include intermittent operation by the power save (PS) control signal and high-speed pull-in that rapidly corrects the phase differences occurring at the start of operation. Pin Assignment XIN XOUT FV VDD DOP VSS VCP FIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OR OV LC FR PS LE DATA CLK Features Low power supply voltage: V DD=1.0 to 1.4V Low power consumption: 0.5mW (V DD=V1.03V, F IN=60MHz) High-speed operation: F IN=60MHz (V DD=1.03V) Frequency dividing ratios in reference frequency dividing stage: 5 to 131,071 Frequency dividing ratios in comparator stage: 272 to 262,143 Lock detector output pin Two types of phase comparator output - Internal charge pump output - Output for external charge pump Output monitor pins for both comparator and reference frequency dividing stages (TOP VIEW) SSOP016-P-0225 MN6153UC Block Diagram XIN 17-bit programmable counter XOUT 17-bit latch CLK 9 2 1 13 FR Phase matching 14 LC Control DATA 10 Data control 18-bit shift register Phase comparator 15 OV 16 OR 7 5 DOP 3 VCP LE 18-bit latch 12 1...