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Input Latch. MC74HC597 Datasheet

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Input Latch. MC74HC597 Datasheet
















MC74HC597 Latch. Datasheet pdf. Equivalent













Part

MC74HC597

Description

8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch



Feature


MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Serial or Parallel-Input/ Serial- Output Shift Register with Input Latch High–Performance Silicon–Gate CMOS The MC54/74HC597 is identical in pinout to the LS597. The device inputs are co mpatible with standard CMOS outputs; wi th pullup resistors, they are compatibl e with LSTTL outputs. This device consi sts of an 8–bit input .
Manufacture

Motorola

Datasheet
Download MC74HC597 Datasheet


Motorola MC74HC597

MC74HC597; latch which feeds parallel data to an 8 bit shift register. Data can also be loaded serially (see Function Table). T he HC597 is similar in function to the HC589, which is a 3–state device. • • • • • • Output Drive Capab ility: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operat ing Voltage Range: 2 to 6 V Low Input C urrent: 1 µA High Noise Immunity C.


Motorola MC74HC597

haracteristic of CMOS Devices In Complia nce with the Requirements Defined by JE DEC Standard No. 7A • Chip Complexity : 516 FETs or 129 Equivalent Gates MC5 4/74HC597 J SUFFIX CERAMIC PACKAGE CASE 620–10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648–08 16 1 D SUFFIX SOIC PACKAGE CASE 751B–05 ORDERING I NFORMATION MC54HCXXXJ MC74HCXXXN MC74HC XXXD Ceramic Plastic SOIC .


Motorola MC74HC597

LOGIC DIAGRAM SERIAL DATA INPUT 14 SA PIN ASSIGNMENT B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A SA SERIAL SHIFT / PARALLEL LOAD LATCH CLOCK SHIFT CLOCK RESET QH A B PARALLEL DATA INPUTS C D E F G H LATCH CLOCK 15 1 2 3 4 5 6 7 12 SERIAL 9 DATA QH OUTPUT INPUT LATCH SHIFT REGISTER C D E F G H GND SHIFT CLOCK SERIAL SHIFT/ PARALLEL LOAD RESET 11 13 10 PIN 16 .





Part

MC74HC597

Description

8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch



Feature


MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Serial or Parallel-Input/ Serial- Output Shift Register with Input Latch High–Performance Silicon–Gate CMOS The MC54/74HC597 is identical in pinout to the LS597. The device inputs are co mpatible with standard CMOS outputs; wi th pullup resistors, they are compatibl e with LSTTL outputs. This device consi sts of an 8–bit input .
Manufacture

Motorola

Datasheet
Download MC74HC597 Datasheet




 MC74HC597
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
with Input Latch
High–Performance Silicon–Gate CMOS
The MC54/74HC597 is identical in pinout to the LS597. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of an 8–bit input latch which feeds parallel data to an
8–bit shift register. Data can also be loaded serially (see Function Table).
The HC597 is similar in function to the HC589, which is a 3–state device.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 516 FETs or 129 Equivalent Gates
SERIAL
DATA
INPUT
SA 14
PARALLEL
DATA
INPUTS
A 15
B1
C2
D3
E4
F5
G6
H7
LATCH CLOCK 12
SHIFT CLOCK 11
SERIAL SHIFT/ 13
PARALLEL LOAD
RESET 10
LOGIC DIAGRAM
INPUT
LATCH
SHIFT
REGISTER
SERIAL
9 QH DATA
OUTPUT
PIN 16 = VCC
PIN 8 = GND
MC54/74HC597
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
B1
C2
16 VCC
15 A
D3
E4
F5
14 SA
13
SERIAL SHIFT/
PARALLEL LOAD
12 LATCH CLOCK
G6
H7
11 SHIFT CLOCK
10 RESET
GND 8
9 QH
10/95
© Motorola, Inc. 1995
1 REV 6




 MC74HC597
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HC597
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 1.5 to VCC + 1.5
– 0.5 to VCC + 0.5
± 20
V
V
mA
DC Output Current, per Pin
± 25 mA
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
± 50
750
500
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg StorageTemperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Ceramic DIP)
– 65 to + 150
260
300
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFor high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC DC Supply Voltage (Referenced to GND)
2.0 6.0 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA Operating Temperature, All Package Types
– 55 + 125 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise and Fall Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
VCC
V
v v– 55 to
25_C
85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH Minimum High–Level Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVoltage
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0 1.5 1.5 1.5
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL Maximum Low–Level Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVoltage
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0 0.3 0.3 0.3 V
4.5 0.9 0.9 0.9
6.0 1.2 1.2 1.2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Minimum High–Level Output
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
Maximum Low–Level Output
Voltage
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout| 4.0 mA
v|Iout| 5.2 mA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout| 4.0 mA
v|Iout| 5.2 mA
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
1.9 1.9
44 44
5.9 5.9
3.84 3.70
5.34 5.20
0.1 0.1
0.1 0.1
0.1 0.1
0.33 0.40
0.33 0.40
V
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin Maximum Input Leakage Current Vin = VCC or GND
6.0 ± 0.1 ± 1.0 ± 1.0 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC MaximumQuiescent Supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 8
80 160 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2 High–Speed CMOS Logic Data
DL129 — Rev 6




 MC74HC597
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfmax
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 8)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Latch Clock to QH
(Figures 1 and 8)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Shift Clock to QH
(Figures 2 and 8)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Reset to QH
(Figures 3 and 8)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to QH
(Figures 4 and 8)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTES:
Maximum Input Capacitance
MC54/74HC597
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
6.0 4.8 4.0
30 24 20
35 28 24
210 265 315
42 53 63
36 45 54
175 220 265
35 44 53
30 37 45
175 220 265
35 44 53
30 37 45
175 220 265
35 44 53
30 37 45
75 95 110
15 19 22
13 16 19
10 10 10
Unit
MHz
ns
ns
ns
ns
ns
pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
50 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs is stored in the
input latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input it Serial
Shift/Parallel Load is high. Data on this input is ignored when
Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied to
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial shifting
is inhibited.
Reset (Pin 10)
Asynchronous, Active–low shift register reset. A low level
applied to this input resets the shift register to a low level, but
does not change the data in the input latch.
Shift Clock (Pin 11)
Serial shift register clock. A low–to–high transition on this
input shifts data on the Serial Data Input into the shift register
and data in stage H is shifted out QH, being replaced by the
data previously stored in stage G.
Latch Clock (Pin 12)
Latch clock. A low–to–high transition on this input loads
the parallel data on inputs A–H into the input latch.
OUTPUT
QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register.
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA




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