MC74HC589

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with 3-State Output High–Performance Silicon–Gate CMOS The MC54/74HC589 is similar in function to the HC597, which is not a 3–state device. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs. This device consists of an 8–bit storage latch which feeds parallel data to an 8–bit shift register. Data can also be loaded serially (see Function Table). The shift register output, QH, is a three–state output, allowing this device to be used in bus–oriented systems. The HC589 directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 526 FETs or 131.5 Equivalent Gates MC54/74HC589 J SUFFIX CERAMIC PACKAGE CASE 620–10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648–08 16 1 D SUFFIX SOIC PACKAGE CASE 751B–05 ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXD Ceramic Plastic SOIC PIN ASSIGNMENT LOGIC DIAGRAM SERIAL DATA INPUT SA 14 B C D E A B PARALLEL DATA INPUTS C D E F G H LATCH CLOCK 15 1 2 3 4 5 6 7 12 9 QH SERIAL DATA OUTPUT DATA LATCH SHIFT REGISTER VCC = PIN 16 GND = PIN 8 F G H GND 1 2 3...