MC74HC564

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Inverting D Flip-Flop High–Performance Silicon–Gate CMOS The MC74HC564 is identical in pinout to the LS564. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is identical in function to the HC534A but has the flip–flop inputs on the opposite side of the package from the outputs to facilitate PC board layout. Data meeting the setup time is clocked, in inverted form, to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip–flops, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be stored even when the outputs are not enabled. The HC564 is the inverting version of the HC574A. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 282 FETs or 70.5 Equivalent Gates 20 MC74HC564 N SUFFIX PLASTIC PACKAGE CASE 738–03 1 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 ORDERING INFORMATION MC74HCXXXN MC74HCXXXDW Plastic SOIC PIN ASSIGNMENT OUTPUT ENABLE D0 D1 D2 D3 D4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK LOGIC DIAGRAM 2 3 4 5 6 7 8 9 11 1 PIN 20 = VCC P...