MC74HC563A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Inverting Transparent Latch High–Performance Silicon–Gate CMOS The MC54/74HC563A is identical in pinout to the LS563. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is identical in function to the HC533A but has the Data Inputs on the opposite side of the package from the outputs to facilitate PC board layout. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The data appears at the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be latched even when the outputs are not enabled. The HC573A is the noninverting version of this function. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 202 FETs or 50.5 Equivalent Gates MC54/74HC563A J SUFFIX CERAMIC PACKAGE CASE 732–03 1 20 20 1 N SUFFIX PLASTIC PACKAGE CASE 738–03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 ORDERING INFORMATION MC54HCXXXAJ Ceramic MC74...