Processor. IBM25PPC440GP Datasheet

IBM25PPC440GP Datasheet PDF


Part

IBM25PPC440GP

Description

PowerPC 440GP Embedded Processor

Manufacture

IBM Microelectronics

Page 30 Pages
Datasheet
Download IBM25PPC440GP Datasheet


IBM25PPC440GP Datasheet
PowerPC 440GP Embedded Processor Data Sheet
Features
• PowerPC® 440 processor core operating up to
500MHz with 32KB I- and D-caches
• On-chip 8 KB SRAM
• Selectable processor:bus clock ratios of 3:1,
4:1, 5:1, 5:2, 7:2
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) 32/64-bit interface operating up to
133 MHz
• External Peripheral Bus for up to eight devices
with external mastering
• DMA support for external peripherals, internal
UART and memory
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI
V2.2
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are
MII, RMII, and SMII.
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT)
• Two serial ports (16750 compatible UART)
• Two IIC interfaces
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• Internal Processor Local Bus (PLB) runs at
DDR SDRAM interface frequency
• Processor can boot from PCI memory
• Available in ceramic and plastic packages
Description
Designed specifically to address high-end
embedded applications, the PowerPC 440GP
(PPC440GP) provides a high-performance, low
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power
management features and lower power dissipation.
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,8KB
SRAM, PCI-X bus interface, Ethernet interfaces,
control for external ROM and peripherals, DMA with
scatter-gather support, serial ports, IIC interface,
and general purpose I/O.
Technology: IBM CMOS SA-27E, 0.18µm
(0.11 Leff), 5-layer metal
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA)
Power (estimated): Less than:
4.0W in normal mode
1.0 W in sleep mode
Supply voltages required: 3.3V, 2.5V, 1.8V
5/13/04
Page 1 of 72

IBM25PPC440GP Datasheet
PowerPC 440GP Embedded Processor Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Heat Sink Mounting Information (Ceramic Package Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Page 2 of 72
5/13/04


Features Datasheet pdf PowerPC 440GP Embedded Processor Data Sh eet Features • PowerPC® 440 processo r core operating up to 500MHz with 32KB I- and D-caches • On-chip 8 KB SRAM • Selectable processor:bus clock rati os of 3:1, 4:1, 5:1, 5:2, 7:2 • Doubl e Data Rate (DDR) Synchronous DRAM (SDR AM) 32/64-bit interface operating up to 133MHz • External Peripheral Bus for up to eight devices with external mast ering • DMA support for external peri pherals, internal UART and memory • P CI-X V1.0a interface (32 or 64 bits, up to 133MHz) with support for convention al PCI V2.2 • Programmable Interrupt Controller supports interrupts from a v ariety of sources. • Programmable Gen eral Purpose Timers (GPT) • Two seria l ports (16750 compatible UART) • Two IIC interfaces • General Purpose I/O (GPIO) interface available • JTAG in terface for board level testing • Int ernal Processor Local Bus (PLB) runs at DDR SDRAM interface frequency • Proc essor can boot from PCI memory • Available in ceramic and plastic packages • Two Ethernet 10/1.
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