Document
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ST20-GP6
GPS PROCESSOR
PRELIMINARY DATA
FEATURES s Application specific features • 12 channel GPS correlation DSP hardware, ST20 CPU (for control and position calculations) and memory on one chip • no TCXO required • RTCA-SC159 / WAAS / EGNOS supported s GPS performance • accuracy - stand alone with SA on <100m, SA off <30m - differential <1m - surveying <1cm • time to first fix - autonomous start 90s - cold start 45s - warm start 7s - obscuration 1s s Enhanced 32-bit VL-RISC CPU - C2 core • 16/33/50 MHz processor clock • 25 MIPS at 33 MHz • fast integer/bit operations s 64 Kbytes on-chip SRAM s 128 Kbytes on-chip ROM s Programmable memory interface • 4 separately configurable regions • 8/16-bits wide • support for mixed memory • 2 cycle external access s Programmable UART (ASC) s Parallel I/O s Vectored interrupt subsystem s Diagnostic control unit s Power management • low power operation • power down modes s Professional toolset support • ANSI C compiler/link driver and libraries • Debugging/profiling and simulation tools s Technology • Static clocked 50 MHz design • 3.3 V, sub micron technology s 100 pin PQFP package s JTAG Test Access Port
December 1998 The information in this datasheet is subject to change
GPS radio ST20-GP6
12 channel GPS hardware DSP
ST20 CPU
Low power controller Real time clock/calendar
Interrupt controller
Serial communications 2 UART (ASC)
Programmable memory interface
Parallel input/output
. . . 16
64K SRAM
Diagnostic control unit
128K optional mask ROM
Test access port
APPLICATIONS s Global Positioning System (GPS) receivers s Car navigation systems s Fleet management systems s Time reference for telecom systems
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ST20-GP6
Contents
1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST20-GP6 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7
Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 DSP module registers ........................................................................................................................... 13
4
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 4.2 4.3 4.4 4.5 4.6 Registers ............................................................................................................................................... 19 Processes and concurrency ................................................................................................................. 20 Priority ................................................................................................................................................... 22 Process communications .........................................................................................................