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AT2004 Dataheets PDF



Part Number AT2004
Manufacturers Atelic Systems
Logo Atelic Systems
Description 4 Channel ADPCM Processor
Datasheet AT2004 DatasheetAT2004 Datasheet (PDF)

AT2004 4 Channels ADPCM Processor with Echo Cancellation and Conferencing Atelic Systems, Inc. AT2004 Application Note Preliminary 4 Channels ADPCM Processor with Echo Cancellation and Conferencing Version 1.0 January 29, 2001 Description The AT2004 is a four full-duplex channels, ADPCM processor with conferencing and echo cancellation capabilities. It follows the G.726 ITU Standard for ADPCM compression for 40k, 32k, 24k and 16k bitrates with selectable µ-law and Alaw input/output. It conforms.

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AT2004 4 Channels ADPCM Processor with Echo Cancellation and Conferencing Atelic Systems, Inc. AT2004 Application Note Preliminary 4 Channels ADPCM Processor with Echo Cancellation and Conferencing Version 1.0 January 29, 2001 Description The AT2004 is a four full-duplex channels, ADPCM processor with conferencing and echo cancellation capabilities. It follows the G.726 ITU Standard for ADPCM compression for 40k, 32k, 24k and 16k bitrates with selectable µ-law and Alaw input/output. It conforms to ITU G.165/G.168 Digital Adaptive Echo Canceller specification for line echo delay up to 20ms. Using the command serial interface, each individual half-channel can be independently configured for ADPCM, conferencing and echo canceling features. Features • • • • • • • • • 4 full channels of ITU G.726 ADPCM 4 full channels of ITU G.165/G.168 complia nt echo cancellation with up to 20ms echo delay Fast and robust convergence for adaptive echo canceller, even in the presence of background noise Nonlinear processing with adaptive suppression threshold and comfort noise generation for echo canceller Per channel selectable µ-Law and A-law input/output On-chip time slot assignment Available internal clock generator and frame sync. generator Simple 3-wire serial command port for chip configuration Conferencing capabilities for up to 3 additional sound sources Applications • • • • DECT VoIP / VoDSL Wireless telephone systems Wireless PBX systems Default Settings • • • • • • 4 channels of µ-law PCM input on Xin in time slot 0, 1, 2, 3 4 channels of the corresponding ADPCM output at 32kbps on Xout in time slot 0, 1, 2, 3 4 channels of ADPCM input at 32kbps on Yin in time slot 0, 1, 2, 3 4 channels of corresponding PCM µ-law output on Yout in time slot 0, 1, 2, 3 Echo cancellation enabled for four channels Conferencing disabled Note: To change the default settings, commands could be sent through the 3-wire interface. Page 1 of 25 ©2001 Atelic System, Inc AT2004 4 Channels ADPCM Processor with Echo Cancellation and Conferencing PIN Description PIN 16 20 27 25 SYMBOL XIN XOUT YIN FSY TYPE I O I I/O DESCRIPTION X Channel Data In . Sampled on the falling edge of CLKP during selected time slots with MSB first. X Channel Data Out. Updated on the rising edge of CLKP during selected time slots with MSB first. Y Channel Data In . Sampled on the falling edge of CLKA during selected time slots with MSB first. Y Channel Frame Sync. Master Y Channel Frame Sync. Signal followed by the first time slot of transmission. It can be either input or output by initial setup sequence. Y Channel Data Out. Updated on the rising edge of CLKA during selected time slots with MSB first. Reset. Low active signal to force chip reset. Crystal In & Out. 14.318 MHz Crystal connected∗∗∗ . PCM Clock . It can be either input created by external control circuit, or output generated by internal control circuit. ADPCM Clock . It can be either input created by external control circuit, or output generated by internal control circuit. Sync 1 . Frame sync. for 1st CODEC. Sync 2 . Frame sync. for 2nd CODEC. Sync 3 . Frame sync. for 3rd CODEC. Sync 4 . Frame sync. for 4th CODEC. TM1 &TM0 . Tie to Ground for normal operation. A1 & A0 . Address ID key for 3-wire serial port. If match, 3-wire serial port can be enabled for configuration. Serial Data In . Data for configuration on the fly by 3-wire serial port. Sampled on the rising edge of SCLK with LSB first. Serial Data Out. Output data after sending Read Memory command by 3-wire serial port. Sampled on the rising edge of SCLK with LSB first. Serial Clock . Used to write to the 3-wire serial port registers or output data from 3-wire serial port registers. Serial Port Chip Select. Low active to enable 3-wire serial port. Power. 3.3 Volts. Ground. 0 Volt. 24 2 13 12 17 26 18 15 11 10 4 3 7 6 22 YOUT RSTZ XTAL1/MCLK XTAL2 CLKP CLKA SYNC1 SYNC2 SYNC3 SYNC4 TM1 TM0 A1 A0 SDI/SDO O I I O I/O I/O O O O O I I I I I/O 21 23 28 14 19 SCLK SCSZ VDD Vss1 Vss2 I I - ∗∗∗ For clock source other than 14.318MHz, please contact Atelic Systems. Page 2 of 25 ©2001 Atelic System, Inc AT2004 4 Channels ADPCM Processor with Echo Cancellation and Conferencing AT2004 PIN Assignment AT2004 SOP Pin Assignment 28-PIN SOP NC RSTZ TM0 TM1 NC A0 A1 NC NC SYNC4 SYNC3 XTAL2 XTAL1 VSS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD YIN CKLA FSY YOUT SCSZ SDI/SDO SCLK XOUT VSS2 SYNC1 CLKP XIN SYNC2 1. 2. When there are multiple AT2004 used on the same system, A1, A0 are used to identify the chip. A1, A0 are for chip ID. Values are from 00 to 03. They should be connected to microcontroller I/O line or hard wired to either VCC or ground. Page 3 of 25 ©2001 Atelic System, Inc AT2004 4 Channels ADPCM Processor with Echo Cancellation and Conferencing AT2004 Function Block Diagram Conferencing up to 3 sources LawP LawA Linear to Law Gain ADPCM Encoder ADPCM Reset M U X ADPCM Bypass Channel Bypass .


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