AT2008 ADPCM Processor Datasheet

AT2008 Datasheet, PDF, Equivalent


Part Number

AT2008

Description

8 Channel ADPCM Processor

Manufacture

Atelic Systems

Total Page 19 Pages
Datasheet
Download AT2008 Datasheet


AT2008
AT2008
8 Channels ADPCM Processor
Atelic Systems, Inc.
Description
AT2008 Application Note Preliminary
8 Channels ADPCM Processor
Version 1.0 January 29, 2001
The AT2008 is an eight full-duplex channels ADPCM processor. It follows the G.726 ITU Standard for ADPCM
compression for 40k, 32k, 24k and 16k bit rates with selectable µ-law and A-law input/output. This chip can operate on 16
channels of PCM to ADPCM compression, 16 channels of ADPCM to PCM decompression, 8 channels of full-duplex
operation in an 8KHz frame basis, or any combination of M-channels of compression plus N-channels of decompression
when M+N <= 16. Using the 3-wire command serial port, each individual half-channel can be dynamically configured to
perform the ADPCM algorithm at different bit rates, idle or reset of the algorithm. It can also be programmed to set up
different input/output time slots, or to select, (1) bypass without compression, (2) idle, or (3) reset of the algorithm.
Features
8 full channels of ITU G.726 ADPCM
ADPCM coding and decoding with bypass mode
Per channel selectable µ-Law and A-law input/output
Up to 8 synchronous signals for direct interface with popular combo/codec.
On-chip time slot assignment
Available internal clock generator and frame sync. generator
Simple 3-wire serial command port for chip configuration
On-chip power-up/power down/reset
The two clock pins (CLKA and CLKP) used as PCM/ADPCM data clocks, and the FSY pin used for Frame Sync signals
can be programmed to become either as input pins or as output pins. (The defaults are as input pins).
Applications
DECT
VoIP / VoDSL
Wireless PBX systems
Default Settings
3-wire serial command is required to configure the chip running ADPCM in 8 full channels.
Page 1 of 19
©2001 Atelic Systems, Inc.

AT2008
PIN Description
AT2008
8 Channels ADPCM Processor
PIN SYMBOL
16 XIN
20 XOUT
27 YIN
25 FSY
24 YOUT
2 RSTZ
13 XTAL1/MCLK
12 XTAL2
17 CLKP
26 CLKA
18 SYNC1
15 SYNC2
11 SYNC3
10 SYNC4
9 SYNC5
8 SYNC6
5 SYNC7
1 SYNC8
4 TM1
3 TM0
7 A1
6 A0
22 SDI/SDO
21 SCLK
23 SCSZ
28 VDD
14 Vss1
19 Vss2
TYPE
I
O
I
I/O
O
I
I
O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I/O
I
I
-
-
-
DESCRIPTION
X Channel Data In. Sampled on the falling edge of CLKP during
selected time slots with MSB first.
X Channel Data Out. Updated on the rising edge of CLKP during
selected time slots with MSB first.
Y Channel Data In. Sampled on the falling edge of CLKA during
selected time slots with MSB first.
Y Channel Frame Sync. Master Y Channel Frame Sync. Signal
followed by the first time slot of transmission. It can be either
input or output by initial setup sequence.
Y Channel Data Out. Updated on the rising edge of CLKA
during selected time slots with MSB first.
Reset. Low active signal to force chip reset.
Crystal In & Out. 14.318 MHz Crystal connected∗∗∗.
PCM Clock. It can be either input created by external control
circuit, or output generated by internal control circuit.
ADPCM Clock. It can be either input created by external control
circuit, or output generated by internal control circuit.
Sync 1. Frame sync. for 1st CODEC.
Sync 2. Frame sync. for 2nd CODEC.
Sync 3. Frame sync. for 3rd CODEC.
Sync 4. Frame sync. for 4th CODEC.
Sync 5. Frame sync. for 5th CODEC.
Sync 6. Frame sync. for 6th CODEC.
Sync 7. Frame sync. for 7th CODEC.
Sync 8. Frame sync. for 8th CODEC.
TM1 &TM0 . Tie to Ground for normal operation.
A1 & A0. Address ID key for 3-wire serial port. If match, 3-wire
serial port can be enabled for configuration.
Serial Data In. Data for configuration on the fly by 3-wire serial
port. Sampled on the rising edge of SCLK with LSB first.
Serial Data Out. Output data after sending Read Memory
command by 3-wire serial port. Sampled on the rising edge of
SCLK with LSB first.
Serial Clock. Used to write to the 3-wire serial port registers or
output data from 3-wire serial port registers.
Serial Port Chip Select. Low active to enable 3-wire serial port.
Power. 3.3 Volts.
Ground. 0 Volt.
∗∗∗For clock source other than 14.318MHz, please contact Atelic Systems.
Page 2 of 19
©2001 Atelic Systems, Inc.


Features AT2008 8 Channels ADPCM Processor Ateli c Systems, Inc. AT2008 Application Note Preliminary 8 Channels ADPCM Processor Version 1.0 January 29, 2001 Descripti on The AT2008 is an eight full-duplex c hannels ADPCM processor. It follows the G.726 ITU Standard for ADPCM compressi on for 40k, 32k, 24k and 16k bit rates with selectable µ-law and A-law input/ output. This chip can operate on 16 cha nnels of PCM to ADPCM compression, 16 c hannels of ADPCM to PCM decompression, 8 channels of full-duplex operation in an 8KHz frame basis, or any combination of M-channels of compression plus N-ch annels of decompression when M+N <= 16. Using the 3-wire command serial port, each individual half-channel can be dyn amically configured to perform the ADPC M algorithm at different bit rates, idl e or reset of the algorithm. It can als o be programmed to set up different inp ut/output time slots, or to select, (1) bypass without compression, (2) idle, or (3) reset of the algorithm. Features • • • • • • • • • 8 ful.
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