CXD304-106Q

CXD304-106Q (1/3) IL00D C-MOS 10-BIT PEDESTAL LEVEL REPLACEMENT OF COMPOSITE SIGNAL —TOP VIEW— 36 35 34 33 32 31 30 29 28 27 26 25 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 GND 37 38 39 40 41 42 43 44 45 46 47 48 GND GND VDD VDD GND 24 23 22 21 20 19 18 17 16 15 14 13 I/O O O O O O – O O O O O O SIGNAL OUT9 OUT8 OUT7 OUT6 OUT5 GND OUT4 OUT3 OUT2 OUT1 OUT0 OPARI PIN NO. 13 14 15 16 17 18 19 20 21 22 23 24 I/O I I I I O – – I I I O O SIGNAL TIN4 TIN3 TIN2 TMOD1 TOUT GND VDD FSC8 CLR DCSY DSSY DRSY PIN NO. 25 26 27 28 29 30 31 32 33 34 35 36 I/O I I I I I I – I I I I I SIGNAL CV9 CV8 CV7 CV6 CV5 CV4 GND CV3 CV2 CV1 CV0 IPARI PIN NO. 37 38 39 40 41 42 43 44 45 46 47 48 I/O I I I I I – – I I I I I SIGNAL OVD TMOD4 TMOD3 TMOD2 GH GND VDD FSC4 TMOD0 PAL / NT TIN1 TIN0 CXD304-106Q (2/3) 35 34 33 32 30 29 28 27 26 25 11 10 9 8 7 5 4 3 2 1 INPUT CV0 CV1 CV2 CV3 CV4 CV5 CV6 CV7 CV8 CV9 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 CLR 36 IPARI OPARI 12 : : CV0 - CV9 : DCSY : FSC4 : FSC8 : GH : IPARI : OVD : PAL / NT : TIN0 - TIN4 TMOD0 - TMOD4 : OUTPUT POWER ON RESET 10-BIT COMPOSITE DATA ANALOG SYNC 4 fsc CLOCK 8 fsc CLOCK GH (GATED H) FROM CXD8819AQ PARITY OF INPUT DATA OUTPUT VD FROM CXD8819AQ H : PAL, L : NTSC TEST PIN : OPEN TEST PIN : OPEN 37 41 OVD GH PAL / NT DRSY DSSY OPARI OUT0 - OUT9 TOUT DSSY DRSY 23 24 46 21 22 20 44 45 16 40 39 38 48 47 15 14 13 : : : : : ANALOG DELAYED SYNC (8 fsc : 56-CLOCK) ANALOG DELAYED ...