Document
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SEPTEMBER 2003
ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
REV. 4.2
GENERAL DESCRIPTION
The ST16C2552 (2552) is a dual universal asynchronous receiver and transmitter (UART). The ST16C2552 is an improved version of the PC16552 UART. The 2552 provides enhanced UART functions with 16 byte FIFOs, a modem control interface, and data rates up to 4 Mbps. Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. Indepedendent programmable baud rate generators are privded to select transmit and receive clock rates from 50 Bps to 4 Mbps. The baud rate generator can be configured for either crystal or external clock input. An internal loop-back capability allows onboard diagnostics. The 2552 provides block mode data transfers (DMA) through FIFO controls. DMA transfer monitoring is provided through the signals TXRDY# and RXRDY#. An Alternate Function Register provides the user with the ability to initialize both UARTs concurrently. The 2552 is available in the 44-PLCC package.
FEATURES
Added feature in devices with top marking "A2 YYWW" and newer:
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5 Volt Tolerant Inputs
• Pin-to-pin and functionally compatible to National
PC16552 and Exar’s XR16L2752 and XR16C2852
• 4 Mbps transmit/receive operation (64 MHz
External Clock Frequency)
• 2 Independent UART Channels
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Register Set Compatible to 16C550 16 byte Transmit FIFO to reduce the bandwidth requirement of the external CPU 16 byte Receive FIFO with error tags to reduce the bandwidth requirement of the external CPU 4 selectable RX FIFO Trigger Levels Fixed Transmit FIFO interrupt trigger level Full Modem Interface (CTS#, RTS#, DSR#, DTR#, RI#, CD#)
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APPLICATIONS
• DMA operation and DMA monitoring via TXRDY#
and RXRDY# pins
• Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls
• UART internal register sections A & B may be
written to concurrently
• Multi-Function
output allows functions with few I/O pins even, odd, or no parity
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package
• Programmable character lengths (5, 6, 7, 8) with • Crystal oscillator or external clock input
FIGURE 1. ST16C2552 BLOCK DIAGRAM
A2:A0 D7:D0 IOR# IOW# CS# CHSEL INTA INTB TXRDYA# TXRDYB# MFA#
(OP2A#, BAUDOUTA#, or RXRDYA#)
3.3V or 5V VCC GND UART Channel A UART Regs BRG 8-bit Data Bus Interface 16 Byte TX FIFO TX & RX 16 Byte RX FIFO RXA (or RXIRA) TXB (or TXIRB) RXB (or RXIRB) Crystal Osc/Buffer Modem Control Logic XTAL1 XTAL2 CTS#A/B, RI#A/B, CD#A/B, DSR#A/B DTR#A/B, RTS#A/B
2552BLK
TXA (or TXIRA)
UART Channel B (same as Channel A)
MFB#
(OP2B#, BAUDOUTB#, or RXRDYB#)
Reset
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO FIGURE 2. PIN OUT ASSIGNMENT
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REV. 4.2
TXRDYA#
DSRA# 41
44
43
42
40
6
5
4
3
2
1
CTSA#
CDA#
RIA#
VCC
D4
D3
D2
D1
D0
D5 D6 D7 A0 XTAL1
7 8 9 10 11
39 38 37 36
RXA TXA DTRA# RTSA#
35 MFA#
GND 12 XTAL2 A1 13 14
ST16C2552 44-pin PLCC
34 33 32 31
INTA VCC TXRDYB# RIB#
A2 15 CHSEL 16 INTB 17 CS# 18 MFB# 19 IOW# 20 RESET 21 GND 22 RTSB# 23 IOR# 24 RXB 25 TXB 26 DTRB# 27 CTSB# 28
30 CDB# 29 DSRB#
ORDERING INFORMATION
PART NUMBER ST16C2552CJ ST16C2552IJ PACKAGE 44-Lead PLCC 44-Lead PLCC OPERATING TEMPERATURE RANGE 0°C to +70°C -40°C to +85°C DEVICE STATUS Active Active
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REV. 4.2
ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME 44-PLCC PIN # TYPE DESCRIPTION
DATA BUS INTERFACE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# 15 14 10 9 8 7 6 5 4 3 2 24 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. UART chip select (active low). This function selects channel A or B in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the 2552. Channel Select - UART channel A or B is selected by the logical state of this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. Normally, CHSEL could just be an address line from the user CPU such as A3. Bit-0 of the Alternate Function Register (AFR) can temporarily override CHSEL.