Document
STARTECH
An Company
ST16C2552
Printed December 17, 1996
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
DESCRIPTION
The ST16C2552 is a dual asynchronous receiver and transmitter with 16 byte transmit and receive FIFOs. Independent programmable baud rate generators are provided to select transmit and receive clock rates from 50Hz to 1.5 MHz for each UART. The on board status registers of the ST16C2552 provide the error conditions, type and status of the transfer operation being performed. Complete MODEM control capability and a processor interrupt system that may be software tailored to the user’s requirements are included. The ST16C2552 provides internal loop-back capability for on board diagnostic testing. Signalling for DMA transfers is done through two pins per channel ( TXRDY*, RXRDY* ). The RXRDY* function is multiplexed on one pin with the OP2* and BAUDOUT functions. CPU can select these functions through the Alternate Function Register. The ST16C2552 is fabricated in an advanced 0.6m CMOS process to achieve low power and high speed requirements.
PLCC Package
TXRDYA* DSRA* 41 CTSA* 40 39 38 37 36 35 CDA* 42 VCC 44 RIA* 43
D4
D3
D2
D1 3
6
5
4
2
D0
D5 D6 D7 A0 XTAL1 GND XTAL2 A1 A2 CHSEL INTB
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1
RXA TXA DTRA* RTSA* MFA* INTA VCC TXRDYB* RIB* CDB* DSRB*
ST16C2552CJ44
34 33 32 31 30 29
CS*
MFB*
IOW*
IOR*
RESET
DTRB* DSRA*
RXB
GND
RTSB*
TXB
FEATURES
TXRDYA*
· Pin to pin and functional compatible to National NS16C552 · 16 byte transmit FIFO · 16 byte receive FIFO with error flags · Modem control signals (CTS*, RTS*, DSR*, DTR*, RI*, CD*) · Programmable character lengths (5, 6, 7, 8) bits · Even, odd, or no parity bit generation and detection · Status report register · TTL compatible inputs, outputs · Independent transmit and receive control · Software compatible with INS8250, NS16C550 · 460.8 kHz transmit/receive operation with 7.372 MHz crystal or external clock source
CTSA* 38
CDA*
VCC
RIA*
CTSB* 37 36 35 34 33 32 31 N.C.
D4
D3
D2
D1 45
48
47
46
44
D0
43
42
41
40
N.C. D5 D6 D7 A0 XTAL1 GND XTAL2 A1 A2 CHSEL INTB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
39
RXA TXA DTRA* RTSA* MFA* INTA VCC TXRDYB* RIB* CDB* DSRB* N.C.
ST16C2552CQ48
30 29 28 27 26 25
CS*
MFB*
IOW*
RTSB*
IOR*
DTRB*
Part number
Package
Operating temperature
ST16C2552CJ44 ST16C2552IJ44
PLCC PLCC
0° C to + 70° C -40° C to + 85° C
Rev. 2.0
3-135
RESET
CTSB*
N.C.
RXB
GND
TXB
ORDERING INFORMATION
ST16C2552
ST16C2552
BLOCK DIAGRAM
D0-D7 IOR* IOW* RESET
Data bus & Control Logic
Transmit FIFO Registers
Transmit Shift Register
TX A/B
Inter Connect Bus Lines & Control signals
Receive FIFO Registers
Receive Shift Register
RX A/B
A0-A2 CS* CHSEL
Register Select Logic
DTR A/B* RTS A/B* MF A/B* Clock & Baud Rate Generator Interrupt Control Logic Modem Control Logic CTS A/B* RI A/B* CD A/B* DSR A/B*
INTA INTB TXRDY* A/B RXRDY* A/B
XTAL1 3-136
XTAL2
ST16C2552
ST16C2552
SYMBOL DESCRIPTION
Symbol D0-D7
Pin 2-9
Signal Type I/O
Pin Description Bi-directional data bus. Eight bit, three state data bus to transfer information to or from the CPU. D0 is the least significant bit of the data bus and the first serial data bit to be received or transmitted. Serial data input A/B. The serial information (data) received from serial port to ST16C2552 receive input circuit. A mark (high) is logic one and a space (low) is logic zero. During the local loopback mode the RX input is disabled from external connection and connected to the TX output internally. Serial data output A/B. The serial data is transmitted via this pin with additional start , stop and parity bits. The TX will be held in mark (high) state during reset, local loopback mode or when the transmitter is disabled. Chip select. (active low) A low at this pin enables the ST16C2552 / CPU data transfer operation. UART A/B select. UART A or B can be selected by changing the state of this pin when CS* is active. Low on this pin, selects the UART B and high on this pin selects UART A section. Crystal input 1 or external clock input. A crystal can be connected to this pin and XTAL2 pin to utilize the internal oscillator circuit. An external clock can be used to clock internal circuit and baud rate generator for custom transmission rates. Crystal input 2 or buffered clock output. See XTAL1. Should be left open if a clcok is connected to XTAL1. Write strobe. (active low) A low on this pin will transfer the contents of the CPU data bus to the addressed register. Read strobe. (active low) A low level on this pin transfers the contents of the ST16C2552 data bus to the CPU. Address select lines. To select internal registers.
RX A/B
39,25
I
TX A/B
38,26
O
CS*
18
I
CHSEL
16
I
XTAL1
11
I
XTAL2
13
O
IOW*
20
I
IOR*
24
I
A0-A2
10,14,15
I
3-137
ST16C2552
ST16C2552 SYMBOL DESCRIPTION
Symbol INT A/B
Pin 34,17
Signal Type .