GS820E32A

GS820E32AT/Q-150/138/133/117/100/66 TQFP, QFP Commercial Temp Industrial Temp Features FT pin for user configurable flow through or pipelined operation. Dual Cycle Deselect (DCD) Operation. 3.3V +10%/-5% Core power supply 2.5V or 3.3V I/O supply. LBO pin for linear or interleaved burst mode. Internal input resistors on mode pins allow floating mode pins. Default to Interleaved Pipelined Mode. Byte write (BW) and/or global write (GW) operation. Common data inputs and data outputs. Clock Control, registered, address, data, and control. Internal Self-Timed Write cycle. Automatic power-down for portable applications. JEDEC standard 100-lead TQFP or QFP package. -150 Pipeline tCycle 6.6ns 3-1-1-1 tKQ 3.8ns IDD 270mA Flow tCycle 10.5ns Through tKQ 9ns 2-1-1-1 IDD 170mA -138 -133 -117 -100 -66 7.25ns 7.5ns 8.5ns 10ns 12.5ns 4ns 4ns 4.5 5ns 6ns 245mA 240mA 210mA 180mA 150mA 15ns 15ns 15ns 15ns 20ns 9.7ns 10ns 11ns 12ns 18ns 120mA 120mA 120mA 120mA 95mA 64K x 32 2M Synchronous Burst SRAM Flow Through / Pipeline Reads 150Mhz - 66Mhz 9ns - 18ns 3.3V VDD 3.3V & 2.5V I/O The function of the Data Output register can be controlled by the user via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FPBGA). Holding the FT mode pin/bump low, places the RAM in Flow through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined Mode, activating the rising edge triggered Data Output Register. DCD Pipelined Reads...