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AT84AS003 Dataheets PDF



Part Number AT84AS003
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description 10-bit 1.5Gsps ADC
Datasheet AT84AS003 DatasheetAT84AS003 Datasheet (PDF)

Features • • • • • • • 10-bit Resolution 1.5 Gsps Sampling Rate Selectable 1:2 or 1:4 Demultiplexed Output 500 mVpp Differential 100Ω or Single-ended 50Ω Analog Input 100Ω Differential or Single-ended 50Ω Clock input LVDS Output Compatibility Functions: – ADC Gain Adjust – Sampling Delay Adjust – 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs – Data Ready Output with Asynchronous Reset – Out-of-range Output Bit (11th Bit) • Power Consumption : 6.5W • Power Supplies: -5V, -2.2V, 3.3V.

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Features • • • • • • • 10-bit Resolution 1.5 Gsps Sampling Rate Selectable 1:2 or 1:4 Demultiplexed Output 500 mVpp Differential 100Ω or Single-ended 50Ω Analog Input 100Ω Differential or Single-ended 50Ω Clock input LVDS Output Compatibility Functions: – ADC Gain Adjust – Sampling Delay Adjust – 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs – Data Ready Output with Asynchronous Reset – Out-of-range Output Bit (11th Bit) • Power Consumption : 6.5W • Power Supplies: -5V, -2.2V, 3.3V and VPLUSD Output Power Supply • Package – Cavity Down EBGA 317 (Enhanced Ball Grid Array) – 25 × 35 mm Overall Dimensions 10-bit 1.5 Gsps ADC With 1:4 DMUX AT84AS003 Summary Performances • • • 3 GHz Full-power Analog Input Bandwidth ±0.4 dB Gain Flatness from DC up to 1.5 GHz Single-tone Performance at Fs = 1.5 Gsps, Full Nyquist Zone – – • – – ENOB = 8.0 Effective Bits, FIN = 750 MHz SNR = 52 dB, SFDR = -60 dBFS, FIN = 750 MHz Fin1 = 745 MHz, Fin2 = 755 MHz: IMD3 = -60 dBFS Fin1 = 1244 MHz, Fin2 = 1255 MHz: IMD3 = -60 dBFS Dual-tone Performance (IMD3) at Fs = 1.5 Gsps (-7 dBFS each tone) Screening • Temperature Range: – – TC > 0°C; TJ < 90°C (Commercial “C” Grade) TC > -20°C; TJ < 110°C (Industrial “V” Grade) Applications • • • • • • Direct RF Down Conversion Ultra Wide Band Satellite Receivers Radars and Countermeasures High-speed Acquisition Systems High Energy Physics Automatic Test Equipment Description The AT84AS003 combines a 10-bit 1.5 Gsps analog-to-digital converter with a 1:4 DMUX, designed for accurate digitization of broadband signals. It features 8.0 Effective Number of Bits (ENOB) and -60 dBFS Spurious Free Dynamic Range (SFDR) at 1.5 Gsps over the full first Nyquist zone. 5403AS–BDC–10/04 This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office. The 1:4 demultiplexed digital outputs are LVDS logic compatible, allowing easy interfacing with standard FPGAs or DSPs .The AT84AS003 operates at up to 1.5 Gsps, without additional tuning of the synchronization between the ADC and DMUX. The AT84AS003 comes in a 25 × 35 mm EBGA317 package. This package has the same TCE as FR4 boards, offering excellent reliability when subjected to large thermal variations. Figure 1. Block Diagram BIST ASYNRST PGEB DRRB SDA 2 CLK/CLKN SDA 20 2 20 Port A AOR/AORN Port B BOR/BORN Port C COR/CORN Port D DOR/DORN DR/DRN LVDS Buffers Logic Block Quantizer 2 20 2 20 2 2 VIN S/H VINN Demultiplexer 1:2 or 1:4 GA B/GB SLEEP STAGG RS DRTYPE 2 AT84AS003 5403AS–BDC–10/04 AT84AS003 Functional Description The AT84AS003 is a 10-bit 1.5 Gsps ADC combined with a high-speed demultiplexer (DMUX) used to lower the LVDS output bit stream (10-bit data and one out-of range bit) by a factor of 2 or 4. The ADC works in fully differential mode from the analog input to the digital outputs. It provides an on-chip 100Ω differential termination for the clock input. The analog input is 500 mVpp on a 100 Ω differential input impedance. 50 Ω reverse terminations are required for the analog input. They should be placed as close as possible to the EBGA package input pins (2 mm maximum). The output clock and the output data are LVDS compatible (100Ω differentially terminated). The AT84AS003 ADC features two asynchronous resets: • • DRRB, which ensures that the first digitized data corresponds to the first acquisition ASYNCRST, which initializes the DMUX The gain control pin GA is used to finely adjust the ADC gain to a unity gain. The control pin B/GB is provided to select either a binary or gray data output format. A Sampling Delay Adjust function (SDA, activated via the SDAEN signal) may be used to fine-tune the ADC aperture delay by approximately 120 ps around its nominal value. This function is useful when interleaving multiple ADCs. The control pin B/GB is provided to select either a binary or Gray data output format. A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX on the clock path to fine-tune the data according to the clock alignment at the interface between the ADC and the DMUX. This delay can be tuned from -250 to 250 ps around a default center value, featuring a 500 ps typical tuning range. No tuning should be necessary for operating frequencies up to 1.5 Gsps. An extra stand-alone delay cell is also provided. It is controlled via analog DACTRL control input and activated via DAEN. The tuning range is typically 500 ps. A pattern generator (PGEB) is integrated in the ADC block for debugging purposes or acquisition setup. Similarly, a Built-in Self Test (BIST) is provided for quick debug of the DMUX block. The demultiplexer ratio can be selected using RS (1:2 or 1:4 ratio). Two modes for the output clock (via DRTYPE) are selectable: • • DR mode: only the output clock’s rising egde is active, the output clock rate is the same as the output data rate DR/2 mode: both the output clock’s rising and fall.


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