IC41C16105 Datasheet PDF


Part Number

IC41C16105

Description

1M X 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Manufacture

ICSI

Total Page 18 Pages
PDF Download
Download IC41C16105 Datasheet PDF


Features Datasheet pdf IC41C16105 IC41LV16105 .EATURES 1M x 16 (16-MBIT) DYNAMIC RAM WITH .AST PAGE M ODE • TTL compatible inputs and output s; tristate I/O • Refresh Interval: 1, 024 cycles/16 ms • Refresh Mode: RAS-O nly, CAS-before-RAS (CBR), Hidden • JE DEC standard pinout • Single power sup ply: 5V ± 10% (IC41C16105) 3.3V ± 10% (IC41LV16105) • Byte Write and Byte R ead operation via two CAS • Industrail temperature range -40oC to 85oC DESCR IPTION The 1+51 IC41C16105 and IC41LV16 105 are 1,048,576 x 16-bit high-perfor mance CMOS Dynamic Random Access Memori es. .ast Page Mode allows 1,024 random accesses within a single row with acces s cycle time as short as 20 ns per 16-b it word. The Byte Write control, of upper and.
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IC41C16105 Datasheet
IC41C16105
IC41LV16105
1M x 16 (16-MBIT) DYNAMIC RAM
WITH .AST PAGE MODE
.EATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 1,024 cycles/16 ms
• Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% (IC41C16105)
3.3V ± 10% (IC41LV16105)
• Byte Write and Byte Read operation via two CAS
• Industrail temperature range -40oC to 85oC
DESCRIPTION
The 1+51 IC41C16105 and IC41LV16105 are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. .ast Page Mode allows 1,024 random accesses
within a single row with access cycle time as short as 20 ns per
16-bit word. The Byte Write control, of upper and lower byte,
makes the IC41C16105 ideal for use in 16-, 32-bit wide data
bus systems.
These features make the IC41C16105 and IC41LV16105
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IC41C16105 and IC41LV16105 are packaged in a
42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. .ast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
-50
50
13
25
20
84
-60 Unit
60 ns
15 ns
30 ns
25 ns
104 ns
PIN CON.IGURATIONS
44(50)-Pin TSOP-2
42-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
15
16
17
18
19
20
21
22
23
24
25
50 GND
49 I/O15
48 I/O14
47 I/O13
46 I/O12
45 GND
44 I/O11
43 I/O10
42 I/O9
41 I/O8
40 NC
36 NC
35 LCAS
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 GND
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 GND
41 I/O15
40 I/O14
39 I/O13
38 I/O12
37 GND
36 I/O11
35 I/O10
34 I/O9
33 I/O8
32 NC
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 GND
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
S2-1




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