ADCMP561

Dual High Speed PECL Comparators ADCMP561/ADCMP562 FEATURES Differential PECL compatible outputs 700 ps propagation delay input to output 75 ps propagation delay dispersion Input common-mode range: –2.0 V to +3.0 V Robust input protection Differential latch control Internal latch pull-up resistors Power supply rejection greater than 85 dB 700 ps minimum pulse width 1.5 GHz equivalent input rise time bandwidth Typical output rise/fall time of 500 ps ESD protection > 4kV HBM, >200V MM Programmable hysteresis FUNCTIONAL BLOCK DIAGRAM HYS* NONINVERTING INPUT Q OUTPUT ADCMP561/ ADCMP562 INVERTING INPUT Q OUTPUT *ADCMP562 ONLY Figure 1. VDD 1 QA 2 04687-0-001 LATCH ENABLE INPUT LATCH ENABLE INPUT 20 VDD 19 QB 18 QB APPLICATIONS Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Line receivers and signal restoration Clock drivers QA 1 QA 2 VDD 3 LEA 4 LEA 5 VEE 6 –INA 7 +INA 8 16 15 14 QB QB GND LEB LEB VCC 04687-0-002 QA 3 VDD 4 LEA 5 LEA 6 VEE 7 –INA 8 +INA 9 HYSA 10 ADCMP562 TOP VIEW (Not to Scale) 17 GND 16 LEB 15 LEB 14 VCC 13 –INB 04687-0-003 ADCMP561 TOP VIEW (Not to Scale) 13 12 11 10 9 –INB +INB 12 +INB 11 HYSB Figure 2. ADCMP561 16-Lead QSOP Figure 3. ADCMP562 20-Lead QSOP GENERAL DESCRIPTION The ADCMP561/ADCMP56...