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IS61LV6464 Dataheets PDF



Part Number IS61LV6464
Manufacturers ISSI
Logo ISSI
Description 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
Datasheet IS61LV6464 DatasheetIS61LV6464 Datasheet (PDF)

IS61LV6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES • Fast access time: – -100 MHz; 6 ns-83 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Five chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 128-Pin TQFP 14mm x 20mm package • Single +3..

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IS61LV6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES • Fast access time: – -100 MHz; 6 ns-83 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Five chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 128-Pin TQFP 14mm x 20mm package • Single +3.3V power supply • 2.5V VDDQ (I/O supply) • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VDDQ to alter their power-up state ISSI ® JANUARY 2004 DESCRIPTION The ISSI IS61LV6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 64 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to eight bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/ O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-I/ O56, BW8 controls I/O57-I/O64, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61LV6464 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VDDQ (or no connect) on MODE pin selects INTERLEAVED Burst. Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 1 IS.


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