ISPPAC-CLK55xx

ispClock 5500 Family ™ In-System Programmable Clock Generator with Universal Fan-Out Buffer August 2004 Data Sheet Features ■ ■ ■ ■ 10MHz to 320MHz Input/Output Operation Low Output to Output Skew (<50ps) Low Jitter Peak-to-Peak(<70ps) Up to 20 Programmable Fan-out Buffers Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL Programmable precision output impedance - 40 to 70Ω in 5Ω increments Programmable slew rate Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V Programmable lock detect Multiply and divide ratio controlled by - Input divider (5 bits) - Internal feedback divider (5 bits) - Five output dividers (5 bits) Programmable On-chip Loop Filter ■ Up to Five Clock Frequency Domains ■ Flexible Clock Reference Inputs Programmable input standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL Clock A/B selection multiplexer Programmable precision termination ■ Four User-programmable Profiles Stored in E2CMOS® Memory Supports both test and multiple operating configurations ■ Fully Integrated High-Performance PLL ■ Full JTAG Boundary Scan Test In-System Programming Support ■ Exceptional Power Supply Noise Immunity ■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges ■ 100-pin and 48-pin TQFP Packages ■ Applications Circuit board common clock generation and distribution PLL-based frequency generation High fan-out clock buffer ■ Precision Programmable Phase Ad...