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SPT5230 Dataheets PDF



Part Number SPT5230
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description 10-BIT / 36 MWPS TRIPLE VIDEO DAC
Datasheet SPT5230 DatasheetSPT5230 Datasheet (PDF)

SPT5230 10-BIT, 36 MWPS TRIPLE VIDEO DAC FEATURES • • • • • • 10-Bit Triple Video Digital-to-Analog Converter Output Full-Scale Voltage 0.5 to 2.0 Vp-p 36 MWPS Operation (typ) Low Power: 280 mW (1 Vp-p Output) 5 V Monolithic CMOS 52-pin QFP Package (10mm x 10mm, 0.65 mm pitch) APPLICATIONS • • • • • Desktop Video Processing CCIR-601 Video Signal Processing RGB Color Monitors Image Processing Direct Digital Synthesis GENERAL DESCRIPTION The SPT5230 is a 10-bit, 36 MWPS triple video digital-toan.

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SPT5230 10-BIT, 36 MWPS TRIPLE VIDEO DAC FEATURES • • • • • • 10-Bit Triple Video Digital-to-Analog Converter Output Full-Scale Voltage 0.5 to 2.0 Vp-p 36 MWPS Operation (typ) Low Power: 280 mW (1 Vp-p Output) 5 V Monolithic CMOS 52-pin QFP Package (10mm x 10mm, 0.65 mm pitch) APPLICATIONS • • • • • Desktop Video Processing CCIR-601 Video Signal Processing RGB Color Monitors Image Processing Direct Digital Synthesis GENERAL DESCRIPTION The SPT5230 is a 10-bit, 36 MWPS triple video digital-toanalog converter specifically designed for high performance, high resolution color graphics monitor applications and video processing applications. A single external resistor controls the full-scale output current. The differential linearity errors of the DACs are guaranteed to be a maximum of ±1.0 LSB over the full temperature range. The device is available in a 52lead QFP package over the commercial temperature range. BLOCK DIAGRAM ROUT AVDD AVDD IOR AVDD IOG GOUT AVDD BOUT IOB VSSA VREF1 VREF VREF2 VCS2 VCS1 VCS Current Switch Cell Array (Cell 4) Current Switch Cell Array (Cell 255) Current Switch Cell Array (Cell 4) Current Switch Cell Array (Cell 255) Current Switch Cell Array (Cell 4) Current Switch Cell Array (Cell 255) Latch Latch Latch Decoder Decoder Decoder Latch Latch Latch (MSB) DG9 DG8 DG7 DG6 DG5 DG4 DG3 DG2 DG1 (LSB) DGØ (MSB) DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 (LSB) DRØ (MSB) DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 (LSB) DBØ CLKG CLKR CLKB ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 Supply Voltages AVDD (measured to AVSS) ........................... –0.3 to 7.0 V Input Voltage Clock and Data ......................................... AVSS to AVDD Output Current IOUT ........................................................................... 0 to 14 mA Temperature Operating, ambient ........................................ 0 to +70 °C Storage ................................................... –55 to + 125 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS fCLK = 27 MWPS, AVDD = 5.0 V, Output Pull-Up Load = 75 Ω, TA = 25 °C, AVSS = 0.0 V PARAMETERS DC Performance Resolution Differential Linearity Integral Linearity Analog Outputs Output Voltage Range Conversion Rate Output Offset Voltage Signal-to-Noise Ratio Settling Time1 Propagation Delay (tpd) Crosstalk FS Control Voltage (VCS2) Digital Inputs and Timing Input Current, Logic High Logic Low Set-Up Time, Data and Controls (tS) Hold Time, Data and Controls (th) Clock Duty Cycle Power Supply Requirements Supply Voltage Supply Current Power Dissipation TEST CONDITIONS TEST LEVEL MIN TYP 10.0 MAX UNITS Bits LSB LSB V MWPS mV dB ns ns dB V µA µA ns ns % V mA mA mW mW TA = TMIN to TMAX I I I I I I I V I V I I I I V I IV I IV I –1.0 –2.5 3.0 27 46 1.0 2.0 5.0 36 2.4 52 16 10 –54 14 23 12 4.0 5 VCS2 = +2.1 V –49 2.0 VIH = 5 V VIL = 0 V –5 5 10 40 4.75 60 5.25 56 100 280 500 1 Vp-p Output 2 Vp-p Output 1 Vp-p Output 2 Vp-p Output 485 1Full-scale settling time to within ±2% of full scale. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 °C. Parameter is guaranteed over specified temperature range. SPT5230 2 5/1/00 INTERFACE CONSIDERATIONS Figure 4 shows a typical interface circuit of the SPT5230 in normal circuit operation. SUPPLY AND GROUND CONSIDERATIONS Fairchild suggests that all power supply pins (AVDD) be tied together and decoupled using a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. EXTERNAL REFERENCE VOLTAGE (VREF1) A +3 V (±10%) voltage reference should be externally generated for the VREF1 pin using the simple voltage divider shown in figure 4. Connect a 0.1 µF bypass capacitor between VREF1 and AVSS as close to the pin as possible. EXTERNAL REFERENCE VOLTAGE (VREF2) VREF2 needs to be externally connected to AVDD through a 1.2 kΩ (5%) resistor. Connect a 0.1 µF bypass capacitor between VREF2 and AVSS as close to the pin as possible. CONTROL VOLTAGE DECOUPLING (VCS1) This is a decoupling pin for the control voltage internal circuitry. An external 0.1 µF capacitor should be connected between VC.


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