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SPT7835 Dataheets PDF



Part Number SPT7835
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description 10-BIT / 5 MSPS / 75 mW A/D CONVERTER
Datasheet SPT7835 DatasheetSPT7835 Datasheet (PDF)

SPT7835 10-BIT, 5 MSPS, 75 mW A/D CONVERTER TECHNICAL DATA JUNE 27, 2001 FEATURES • • • • • • • • • • Monolithic 5 MSPS converter 75 mW power dissipation On-chip track-and-hold Single +5 V power supply TTL/CMOS outputs 5 pF input capacitance Low cost Tri-state output buffers High ESD protection: 3,500 V minimum Selectable +3 V or +5 V logic I/O APPLICATIONS • All high-speed applications where low power dissipation is required • Video imaging • Medical imaging • IR imaging • Scanners • Digital .

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SPT7835 10-BIT, 5 MSPS, 75 mW A/D CONVERTER TECHNICAL DATA JUNE 27, 2001 FEATURES • • • • • • • • • • Monolithic 5 MSPS converter 75 mW power dissipation On-chip track-and-hold Single +5 V power supply TTL/CMOS outputs 5 pF input capacitance Low cost Tri-state output buffers High ESD protection: 3,500 V minimum Selectable +3 V or +5 V logic I/O APPLICATIONS • All high-speed applications where low power dissipation is required • Video imaging • Medical imaging • IR imaging • Scanners • Digital communications GENERAL DESCRIPTION The SPT7835 is a 10-bit monolithic, low-cost, ultralowpower analog-to-digital converter capable of minimum word rates of 5 MSPS. The on-chip track-and-hold function assures very good dynamic performance without the need for external components. The input drive requirements are minimized due to the SPT7835’s low input capacitance of only 5 pF. Power dissipation is extremely low at only 75 mW typical at 5 MSPS with a power supply of +5.0 V. The digital outputs are +3 V or +5 V, and are user selectable. The SPT7835 is pin-compatible with an entire family of 10-bit, CMOS converters (SPT7835/40/50/55/60/61), which simplifies upgrades. The SPT7835 has incorporated proprietary circuit design* and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS-compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The SPT7835 is available in a 28-lead SOIC package over the industrial temperature range, and a 32-lead small (7 mm square) TQFP package over the commercial temperature range. *Patent pending BLOCK DIAGRAM ADC Section 1 AIN 1:8 Mux T/H AutoZero CMP 11-Bit SAR 11 11 D10 Overrange D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 P1 P2 Timing P7 and Control Enable P8 DAC CLK In . . . . . . ADC Section 7 ADC Section 2 ADC Section 8 T/H AutoZero CMP . . . 11-Bit SAR 11 DAC 11 . . . 11 11 11-Bit 8:1 Mux/ Error Correction Data Valid Ref In Reference Ladder D0 (LSB) VREF ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages AVDD ...................................................................... +6 V DVDD ..................................................................... +6 V Input Voltages Analog Input .............................. –0.5 V to AVDD +0.5 V VREF .............................................................. 0 to AVDD CLK Input ............................................................... VDD AVDD – DVDD .................................................. ±100 mV AGND – DGND .............................................. ±100 mV Output Digital Outputs ................................................... 10 mA Temperature Operating Temperature ............................ –40 to 85 °C Junction Temperature ........................................ 175 °C Lead Temperature, (soldering 10 seconds) ....... 300 °C Storage Temperature ............................ –65 to +150 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒCLK=10 MHz, ƒS=5 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Linearity Error (ILE) Differential Linearity Error (DLE) No Missing Codes Analog Input Input Voltage Range Input Resistance Input Capacitance Input Bandwidth Offset Gain Error Reference Input Resistance Bandwidth Voltage Range VRLS VRHS VRHS – VRLS ∆(VRHF – VRHS) ∆(VRLS – VRLF) Reference Settling Time VRHS VRLS Conversion Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits (ENOB) ƒIN = 1 MHz Signal-to-Noise Ratio (SNR) (without Harmonics) ƒIN = 1 MHz TEST CONDITIONS TEST LEVEL MIN 10 SPT7835 TYP MAX UNITS Bits VI VI VI VI IV V V V V VI V IV IV V V V V V VI IV IV V V 5 2 VRLS 50 ±1.0 ±0.5 Guaranteed VRHS 5.0 100 ±2.0 ±2.0 400 100 0 3.0 1.0 500 150 600 2.0 AVDD 5.0 LSB LSB (Small Signal) V kΩ pF MHz LSB LSB Ω MHz V V V mV mV Clock Cycles Clock Cycles MHz MHz Clock Cycles ns ps (p-p) 4.0 90 75 15 20 12 5 10 VI VI 54 9.2 59 Bits dB SPT7835 2 6/27/01 ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒCLK=10 MHz, ƒS=5 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Dynamic Performance Total Harmonic Distortion (THD) ƒIN = 1 MHz Signal-to-Noise and Distortion (SINAD) ƒIN = 1 MHz Spurious Free Dynamic Range Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage tRISE tFALL Output Enable to Data Output Delay Power Supply Requirements Voltages OVDD DVDD AVDD Currents AIDD DIDD Power Dissipation TEST CONDITIONS TEST LEVEL MIN SPT7835 TYP MAX UNITS VI VI V VI .


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