ICS8305

Integrated Circuit Systems, Inc. ICS8305 LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER FEATURES 4 LVCMOS/LVTTL outputs Selectable differential or LVCMOS/LVTTL clock inputs CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL LVCMOS_CLK supports the following input types: LVCMOS, LVTTL Maximum output frequency: 350MHz Output skew: 35ps (maximum) Part-to-part skew: 700ps (maximum) Additive phase jitter, RMS: 0.04ps (typical) 3.3V core, 3.3V, 2.5V or 1.8V output operating supply 0°C to 70°C ambient operating temperature Industrial temperature information available upon request GENERAL DESCRIPTION The ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. ICS Guaranteed output and part-to-part skew characteristics make the ICS8305 ideal for those applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK_EN D Q LE LVCMOS_CLK C...