CY7C149

CY7C148 CY7C149 1Kx4 Static RAM Features Automatic power-down when deselected (7C148) CMOS for optimum speed/power 25-ns access time Low active power — 440 mW (commercial) sion is provided by an active LOW chip select (CS) input and three-state outputs. The CY7C148 remains in a low-power mode as long as the device remains unselected; i.e., (CS) is HIGH, thus reducing the average power requirements of the device. The chip select (CS) of the CY7C149 does not affect the power dissipation of the device. Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the I/O pins (I/O 0 through I/O 3) is written into the memory locations specified on the address pins (A 0 through A 9). Reading the device is accomplished by taking chip select (CS) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the four data I/O pins. The I/O pins remain in a high-impedance state when chip select (CS) is HIGH or write enable (WE) is LOW. — 605 mW (military) Low standby power (7C148) — 82.5 mW (25-ns version) — 55 mW (all others) 5-volt power supply ± 10% tolerance, both commercial and military TTL-compatible inputs and outputs Functional Description The CY7C148 and CY7C149 are high-performance CMOS static RAMs organized as 1024 by 4 bits. Easy memory expan- Logic Block Diagram Pin Configurations DIP Top View A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 1...