MN3880S

CCD Delay Line Series MN3880S NTSC CCD Video Signal Delay Element Overview The MN3880S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, two CCD delay elements, a clamp bias circuit, resampling output amplifiers, and booster circuits. The MN3880S samples the input using the supplied clock signal with a frequency of 7.15909 MHz, twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment VBIASC VOC N.C. VDD –VBB N.C. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VINC N.C. N.C. X1 VSS N.C. N.C. VINY Features Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for chrominance signal after passing through a low pass filter VOY VBIASY (TOP VIEW) SOP016-P-0225 Applications VCRs 1 MN3880S Block Diagram CCD Delay Line Series 12 4 Bias circuit VINC 16 Charge input block Charge detection block Resampling output amplifier 2 CCD 454 stages 1 VBIASC VDD VSS VOC øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver Timing adjustment XI 13 Waveform amplitude adjustment block Timing adjustment øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver Clamp circuit VINY 9 Charge input block 5 Charge detection block Resampling output amplifier 8 7 VOY CCD 454 stages –...