HY5DU121622B

HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP 512Mb DDR SDRAM HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.1 / May 2004 1 HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP Revision History Revision No. 0.1 History Initial Draft Draft Date May 2004 Remark Rev. 0.1 / May 2004 2 HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP DESCRIPTION The HY5DU12422B(L)TP, HY5DU12822B(L)TP and HY5DU121622B(L)TP are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous...