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M-8870 Dataheets PDF



Part Number M-8870
Manufacturers Clare
Logo Clare
Description DTMF Receiver
Datasheet M-8870 DatasheetM-8870 Datasheet (PDF)

M-8870 DTMF Receiver · · · · · · · · Low power consumption Adjustable acquisition and release times Central office quality and performance Power-down and inhibit modes (-02 only) Inexpensive 3.58 MHz time base Single 5 volt power supply Dial tone suppression Applications include: telephone switch equipment, remote data entry, paging systems, personal computers, credit card systems The M-8870 is a full DTMF Receiver that integrates both bandsplit filter and decoder functions into a single 18-p.

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M-8870 DTMF Receiver · · · · · · · · Low power consumption Adjustable acquisition and release times Central office quality and performance Power-down and inhibit modes (-02 only) Inexpensive 3.58 MHz time base Single 5 volt power supply Dial tone suppression Applications include: telephone switch equipment, remote data entry, paging systems, personal computers, credit card systems The M-8870 is a full DTMF Receiver that integrates both bandsplit filter and decoder functions into a single 18-pin DIP or SOIC package. Manufactured using CMOS process technology, the M-8870 offers low power consumption (35 mW max) and precise data handling. Its filter section uses switched capacitor technology for both the high and low group filters and for dial tone rejection. Its decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4bit code. External component count is minimized by provision of an on-chip differential input amplifier, clock generator, and latched tri-state interface bus. Minimal external components required include a low-cost 3.579545 MHz color burst crystal, a timing resistor, and a timing capacitor. Figure 1 Pin Connections The M-8870-02 provides a “power-down” option which, when enabled, drops consumption to less than 0.5 mW. The M-887002 can also inhibit the decoding of fourth column digits (see Table 5). Figure 2 Block Diagram 40-406-00011, Rev. F Page 1 www.clare.com M-8870 Functional Description M-8870 operating functions (see Figure 2) include a bandsplit filter that separates the high and low tones of the received pair, and a digital decoder that verifies both the frequency and duration of the received tones before passing the resulting 4-bit code to the output bus. Filter The low and high group tones are separated by applying the dual-tone signal to the inputs of two 6th order switched capacitor bandpass filters with bandwidths that correspond to the bands enclosing the low and high group tones. The filter also incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor section that smooths the signals prior to limiting. Signal limiting is performed by high-gain comparators provided with hysteresis to prevent detection of unwanted low-level signals and noise. The comparator outputs provide full-rail logic swings at the frequencies of the incoming tones. Decoder The M-8870 decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while tolerating small frequency variations. The algorithm ensures an optimum combination of immunity to talkoff and tolerance to interfering signals (third tones) and noise. When the detector recognizes the simultaneous presence of two valid tones (known as “signal condition”), it raises the Early Steering flag (ESt). Any subsequent loss of signal condition will cause ESt to fall. Steering Circuit Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as “character-recognition-condition”). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes VC (see Figure 2) to rise as the capacitor discharges. Provided that signal condition is maintained (ESt remains high) for the validation period (tGTF), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, thus latching its corresponding 4-bit code (see Table 3) into the output latch. At this point, the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the “delayed steering” output flag (StD) goes high, signaling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three-state control input (OE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropouts) too short to be considered a valid pause. This capability, together with the ability to select the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Figure 4 Single-Ended Input Configuration Guard Time Adjustment Where independent selection of signal duration and interdigit pause are not required, the simple steering circuit of Figure 3 is applicable. Component values are chosen according to the formula: tREC = tDP + tGTP tGTP ≅ 0.67 RC The value of tDP is a parameter of the device and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 µF is recomme.


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