MBM29F016A

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20844-4E FLASH MEMORY CMOS 16M (2M × 8) BIT MBM29F016A-70/-90/-12 s FEATURES Single 5.0 V read, write, and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection 48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) Minimum 100,000 write/erase cycles High performance 70 ns maximum access time Sector erase architecture Uniform sectors of 64 K bytes each Any combination of sectors can be erased. Also supports full chip erase. Embedded Erase™ Algorithms Automatically pre-programs and erases the chip or any sector Embedded Program™ Algorithms Automatically programs and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion Low VCC write inhibit ≤ 3.2 V Hardware RESET pin Resets internal state machine to the read mode Erase Suspend/Resume Supports reading or programming data to a sector not being erased Sector group protection Hardware method that disables any combination of sector groups from write or erase operation (a sector group consists of 4 adjacent sectors of 64 K bytes each) Temporary sector groups unprotection Temporary sector unprotection via the RESET pin Embedded Erase™, Embedded Progr...