MBM29LV080A

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20870-4E FLASH MEMORY CMOS 8M (1M × 8) BIT MBM29LV080A-70/-90/-12 s FEATURES Address specification is not necessary during command sequence Single 3.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard world-wide pinouts 40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type) Minimum 100,000 program/erase cycles (Continued) s PRODUCT LINE UP Part No. VCC = 3.3 V Ordering Part No. VCC = 3.0 V Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) +0.3 V –0.3 V +0.6 V –0.3 V MBM29LV080A -70 — 70 70 30 — -90 90 90 35 — -12 120 120 50 s PACKAGE 40-pin plastic TSOP (I) Marking Side 40-pin plastic TSOP (I) Marking Side (FPT-40P-M06) (FPT-40P-M07) MBM29LV080A-70/-90/-12 (Continued) High performance 70 ns maximum access time Sector erase architecture 16 sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector Embedded programTM* Algorithms Automatically programs and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion Automatic sleep mode...